SRP: Current Status

1. SRP: Current Status Irakli MANDJAVIDZE DAPNIA, CEA Saclay,91191 Gif-sur-Yvette, France Irakli.MANDJAVIDZE@cea.fr

2. Overview • Hardware • Firmware • Plans Irakli.MANDJAVIDZE@cea.fr

3. Hardware • Schematic capture in progress • Already done • VME • JTAG • TTCrx & QPLL • Parallel optic modules • To be done • Clock circuitry • Configuration Flash PROMs • TTS interface • External Memory • Ethernet and RS232 console • Power circuitry Irakli.MANDJAVIDZE@cea.fr

4. Targeted AB Test-bed • Debugging and testing of ABs with ABs ABundertest ABtester CC SBS620 TTCVI TTCEX DCC emulatorup to 6 chan. Control PC TCCRX DCCRX DCCTX TCCTX ABRX ABRX TCC emulatorup to 12 chan. LinuxHALXDAQ DAQKit ABTX ABTX sTTSIN sTTSIN TTCOUT sTTSOUT sTTSOUT Attenuator Attenuator TTCIN TTCIN Irakli.MANDJAVIDZE@cea.fr

5. Firmware Architecture • System-on-chip design • Embedded PowerPC processor for control and monitoring • Facilitates debugging and testing • Currently standalone “C” application RS232Console User Logic PPC100 MHz Application e.g. AB orAB Tester Ethernet On-chip Peripheral Bus On-chipmemory Processor Local Bus: 50 MHz LocalBus VME Bridge SlaveInterface Arbiter Irakli.MANDJAVIDZE@cea.fr

6. Firmware Debugging • Firmware is tested on 3 Virtex-2 Pro development boards • TCS emulation : with 2VP7 device • AB Tester : with 2VP30 device • 8 RocketIOs • AB: with 2VP50 device • 8 RocketIOs TCS Emulator (2vp7) Flat ribbon cablefor TCS signals N TCC and DCC links AB Tester (2VP30) AB (2VP50) M AB links Irakli.MANDJAVIDZE@cea.fr

7. TCS Emulator Firmware • Generates and distributes TTC signals • Clock40 • L1Accept • BGo commands • Receives and combines sTTS signals • From AB and AB Tester • Implements TCS state machine • As in CMS NOTE 2002/033 • Allows to start/stop run from console • At any state changes fill a Spy buffer • Monitoring and debugging • Signals follow closely TTCrx pin-out • AB and AB tester feel like getting data from TTCrx Irakli.MANDJAVIDZE@cea.fr

8. TCS Emulator Screen Dump Irakli.MANDJAVIDZE@cea.fr

9. AB Tester Firmware • Sender module • Memory with pre-loaded data to be sent at L1 Accept • TCC: TT classification flags • AB: Frontier TT classification flags • Receiver module • Memory with pre-loaded data to be received • DCC: SR flags • AB: Frontier TT classification flags • Memory to store erroneous events • Wrong sender, event ID or data • Parity or transmission error • Communication channels • DCC/TCC: 80 MHz – 1.6 Gbit/s • AB: up to 100 MHz – 2.0 Gbit/s • Variable number of TCC/DCC and AB/AB instances • Usually running with 4 DCC/TCC and with 4 AB/AB Irakli.MANDJAVIDZE@cea.fr

10. AB Tester Firmware (cont.) • TCS module • Receives 40 MHz TTC Clock • Receives and interprets BGo commands • Receives and buffers L1 Accepts • Transmits sTTS signals • AB Tester State Machine • L1_Enb, L1_Wait, Arm_Time_Out, Wait_for_data, Disarm_Time_Out, Error • Run Control State Machine • On, Init, Idle, Running, Out_of_Sync, Error • Spy Memory • At any STATUS register changes • VME interface: to be done Same firmware to test barrel and endcap ABs Irakli.MANDJAVIDZE@cea.fr

11. AB Tester Screen Dump • General status and TTC module statistics Irakli.MANDJAVIDZE@cea.fr

12. Sender and Receiver module statistics AB Tester Screen Dump (Forced) data content errors • Communication channels statistics Irakli.MANDJAVIDZE@cea.fr

13. AB Tester Screen Dump • Spy memory Irakli.MANDJAVIDZE@cea.fr

14. Algorithm Board Firmware • Under development • Shares many modules with AB Tester • TCS • Run Control state machine • Clock management • Communication channels • VME Interface • SoC • Modules developed for the system R&D work to be reused • e.g. Multi-port memory • Two types of firmware • for barrel AB • for endcap AB Irakli.MANDJAVIDZE@cea.fr

15. Plans • Two AB prototypes in September • Standalone debugging and testing until December • System-wide tests starting from 2006 • Production, installation, integration, commissioning in 2006 • At least for barrel Irakli.MANDJAVIDZE@cea.fr