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Inner PF Coil Design Updated

Inner PF Coil Design Updated. C Neumeyer 2/2/10. Changes Since Prior Version. Added electrical insulation Account for 3-wire system ground fault Account for CHI voltage (PF1a, PF1b only) Re-optimized conductor size and turns in PF1b and PF1c

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Inner PF Coil Design Updated

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  1. Inner PF Coil DesignUpdated C Neumeyer 2/2/10

  2. Changes Since Prior Version • Added electrical insulation • Account for 3-wire system ground fault • Account for CHI voltage (PF1a, PF1b only) • Re-optimized conductor size and turns in PF1b and PF1c • Necessary to use unique conductor cross sections in all three coils (PF1a, PF1b, PF1c) • Preserving conductor similarity in PF1b and PF1c resulted in too much performance reduction in PF1c (already underperforming on ESW basis)

  3. Design Considerations • Constraints • Amp-turns per J. Menard • Fit in existing R, Z, dR, dZ per J. Chrz • Use same conductor size in PF1b and PF1c • Design variables • PS voltage (1kV or 2kV) • Turn and ground insulation thickness • Number of layers and turns • Cooling hole diameter • Design objectives • Favoring increase in #turns • rms ripple current < 1% of peak current w/o external filter inductor • Transrex current < 24kA and to be minimized • Favoring decrease in #turns • Packing factor and ESW capability • dI/dt in PF1b and PF1c > 35kA-turn/mS for CHI • Forcing factors (V-I*R)/L > existing PF1a and PF1b • Voltage induced from OH < 50% of PS voltage • Worst case induced voltage ~ Transrex Vdc =1012V << Transrex Vdc_MOV*4 ~ 2.4kV • Cooldown time <= 1200s with 400psi pressure drop No change since prior version

  4. Methodology • NSTX_CSU_Design Spreadsheet • Input geometry, turns, insulation, etc. • Calculate flow/pressure drop, ESW, self-inductance, ripple current, Idot, etc. • Mutual inductance matrix • Calculate mutual inductance matrix using ICC • Estimate max induced voltage • assuming I_dot = V/L in each circuit independently • Calculate sum of M*I_dot as if each coil open circuited while others at max I_dot • Use XL solver to find turns adjuatment ratio in PF1a/b/c to minimize largest induced voltage • Constrain turns such that Transrex PS current < 24kA • Recalculate M matrix using ICC • Determine voltage induced from OH = M*Ioh_dot • Worst case induced voltage • Run LRSIM with all circuit at Vmax except one open at a time • Cooldown time • Run KCOOL • Evaluate results and iterate No change since prior version

  5. Summary of New Design 1 – max ripple (amp rms/rated current) occurs in 1kV, 6-pulse configuration 2 – min forcing factor ocurrs in 1kV configuration 3 – max slew rate based on 2kV configuration

  6. Conductors Was not able to use common conductor for PF1b and PF1c

  7. Power Supplies PF1a 2kV@+5kA/-22kA - + D D Y Y PF1b (upgrade 1) 2kV@ +8kA PF1b (upgrade 2) 1kV@ +/-8kA or 2kV@ +8kA PF1c (upgrade 1) 2kV@ +13kA PF1c (upgrade 2) 1kV@ +/-18kA or 2kV@ +18kA D Y D Y

  8. Summary • Inner PF coil designs revised • Meet req’ts except • ESW < 5.5s on PF1a & PF1c • Upgrade path exists based on Transrex PS • Ready for design point revision • Need influence matrix update (R Hatcher) • Need equilibria update (J Menard) • Will post on web as open revision

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