The Control Unit of Tiny Mips Processor

1. The Control Unit of TinyMips Processor

2. Processor Input Control Memory Datapath Output DATAPATH Tiny Mipsreview and completion as prep for the control Digital Techniques Fall 2007 André Deutz, Leiden University

3. 4 4 2 4 2 4 4 Fetch part of the datapath for Tiny Mips PC + D D Q alu 1 opcode address Instruction memory opcode alu Digital Techniques Fall 2007 André Deutz, Leiden University

4. Fetch part of the datapath for Tiny Mips Fetch part accommodates also branching Digital Techniques Fall 2007 André Deutz, Leiden University

5. PC + D 4 4 3 4 4 4 1 4 4 4 2 2 Q alu 1 control D opcode address 2-bit first operand info Instruction memory 2-bit second operand info Sel Reg For Read Port A Sel Write Reg Port A opcode alu Sel Reg For Read Port B WriteReg we Write data Port B alu Register File Four 4-bit regs Datapath for add, sub, or, and, not for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

6. PC + D 4 4 3 4 4 4 2 4 1 4 2 4 Q alu 1 control D opcode address 2-bit first operand info Instruction memory 2-bit second operand info Sel Reg For Read Port A Sel Write Reg ALU operation Port A opcode alu Sel Reg For Read Port B WriteReg we Write data Port B alu Register File Four 4-bit regs Datapath for add, sub, or, and, not for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

7. Datapath for add, sub, or, and, not for Tiny Mips in Digital Works Fetch Part accommodates Branching Digital Techniques Fall 2007 André Deutz, Leiden University Digital Techniques Fall 2007 André Deutz, Leiden University

8. PC + D 1 2 3 1 4 4 4 2 2 4 4 4 4 4 Q alu 1 control D opcode address 2-bit first operand info Instruction memory 2-bit second operand info Accommodates ldi Accommodates ldui ALUsource Sel Reg For Read Port A Sel Write Reg ALU operation Port A opcode alu mux Sel Reg For Read Port B 0 WriteReg we Write data ALUsource alu Register File Four 4-bit regs Port B mux mux 0 Datapath for add, sub, or, and, not, ldi, ldui, mv for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

9. PC + D 4 4 1 3 4 2 4 1 4 4 4 4 2 2 Q alu 1 control D opcode address 2-bit first operand info Instruction memory 2-bit second operand info ALUsource Sel Reg For Read Port A Sel Write Reg ALU operation Port A opcode alu mux Sel Reg For Read Port B 0 WriteReg we Write data ALUsource alu Register File Four 4-bit regs Port B mux mux 0 Datapath for add, sub, or, and, not, ldi, ldui, mv for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

10. Datapath for add, sub, or, and, not, ldi, ldui, mv for Tiny Mips Digital Works (includes also breq and unconditional jump, see Also next slide for this) Digital Techniques Fall 2007 André Deutz, Leiden University Digital Techniques Fall 2007 André Deutz, Leiden University

11. PC + D 1 3 4 4 2 2 4 1 4 4 4 4 2 Q alu 1 control 4 opcode address first operand info Br Uncond Instruction memory second operand info setEqual clock BreqSwitch ALU operation ALUsource Sel Reg For Read Port A Sel Write Reg Port A alu mux Sel Reg For Read Port B 0 WriteReg we EQ Write data ALUsource D Register File Four 4-bit regs Port B Q mux mux mux 0 Datapath for add, sub, or, and, not, ldi, ldui,mv, breq, br for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

12. PC + D 4 3 4 4 2 2 4 1 1 4 4 4 2 Q alu 1 4 opcode address first operand info Br Uncond Instruction memory control second operand info setEqual clock BreqSwitch Sel Reg For Read Port A Sel Write Reg Port A alu mux Sel Reg For Read Port B 0 we EQ Write data D Register File Four 4-bit regs Port B Q mux mux mux 0 Datapath for add, sub, or, and, not, ldi, ldui, mv, breq, br for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

13. PC + D 4 3 4 4 4 2 2 4 4 4 4 4 2 1 1 Q alu 1 control D opcode address 2-bit first operand info Instruction memory 2-bit second operand info ALU operation WriteMem ALUsource MemToReg Sel Reg For Read Port A Sel Write Reg Port A opcode alu mux Read Data Sel Reg For Read Port B 0 Address WriteReg we Write data ALUsource alu Data Memory Write Data Register File Four 4-bit regs Port B mux mux 0 ReadMem Datapath for add, sub, or, and, not, ldi, ldui,mv, ld, st for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

14. PC + D 3 4 4 4 4 2 2 4 4 4 4 4 1 2 1 Q alu 1 control D opcode address 2-bit first operand info Instruction memory 2-bit second operand info ALU operation WriteMem ALUsource MemToReg Sel Reg For Read Port A Sel Write Reg Port A opcode alu mux Read Data Sel Reg For Read Port B 0 Address WriteReg we Write data ALUsource alu Data Memory Write Data Register File Four 4-bit regs Port B mux mux 0 ReadMem Datapath for add, sub, or, and, not, ldi, ldui, mv,ld, st for Tiny Mips Digital Techniques Fall 2007 André Deutz, Leiden University

15. Data path Tiny Mips • Merge the two previous data paths to get the full data path for TM Digital Techniques Fall 2007 André Deutz, Leiden University

16. Control for Tiny Mipswhich is single cycle • How do we construct the control unit? • Wc can specify the control with Truth Tables • Disadvantages of single cycle • Control for multi-cycle processor the control is specified by • FSM (finite state machine), or alternatively • Microprogramming Digital Techniques Fall 2007 André Deutz, Leiden University

17. Control Macro for TM Digital Techniques Fall 2007 André Deutz, Leiden University

18. Tiny Mips Processor Digital Techniques Fall 2007 André Deutz, Leiden University