Introduction to HDLs

1. Introduction to HDLs • HDL (Hardware Description Language) • VHDL versus Verilog • IC world only uses Verilog

2. How do IC designers use Verilog? • Can be used for simulation • Simulation at behavioral level, gate level, and at the switch level! • Can be used for circuit synthesis • Can be used to verify post-synthesis timing

3. Why Verilog and not VHDL? • C-like syntax (as opposed to Pascal-like!) • Better for circuit synthesis • I feel it is easier to create testbenches but others will dispute this claim! • Switch-level descriptions supported • Timing is more easily included • Can link in you own C-code!

4. Verilog Coding Styles • Behavioral Descriptions • Dataflow Descriptions • Gate-Level Descriptions (netlist) • Switch-Level Descriptions

5. Verilog Basics • Case-sensitive!!!!! • No special characters in variable names except _ • Variable names must start with alpha character • Free-form • Very C-like

6. Concurrent Versus Sequential • Separate syntax to support descriptions of concurrent and sequential activity • Concurrent constructs best for describing combinational circuits • Sequential constructs must be used for describing sequential networks and for writing testbenches … MAY be used for combinational circuits BUT BE CAREFUL!

7. First Example // // First example // module first_example(f, x, y, z) ; input x, y, z ; output f ; assign f = (x & y & ~z) | (x & ~y & z) | (~x & ~y & ~z) ; endmodule

8. First Example Testbench // // Testbench for first example // `timescale 1ns/100ps module first_example_tb ; reg x, y, z ; wire f ; integer fid ; first_example u0(f, x, y, z) ; initial begin fid = $fopen("./first_example.out") ; $fmonitor(fid, $time, " x = %b, y = %b, z = %b, f = %b", x, y, z, f) ; #100 x = 1'b0 ; y = 1'b0 ; z = 1'b0 ; #100 x = 1'b1 ; y = 1'b1 ; z = 1'b0 ; #100 x = 1'b1 ; y = 1'b1 ; z = 1'b1 ; #100 $finish ; end endmodule

9. Running Verilog XL To simulate “first example” do the following: % verilog first_example_tb.v first_example.v OR Create a file called, for example, “modules” and on separate Lines place the two filenames from above and give the Command % verilog –f modules

10. 8-bit Counter // // Up-down counter // module cnt8bit(cnt, tc, up, down, clr, ld, clk, inp) ; input up, down, clr, ld, clk ; input [7:0] inp ; output tc ; output [7:0] cnt ; reg [7:0] cnt ; assign tc = (&cnt & up) | (&(~cnt) & down) ; always @(posedge clk or posedge clr) begin if (clr) cnt <= 8'd0 ; else if (ld) cnt <= inp ; else if (up) cnt <= cnt + 8'd1 ; else if (down) cnt <= cnt - 8'd1 ; else cnt <= cnt ; end endmodule

11. Testbench for counter // // Up-down counter testbench // module cnt8bit_tb ; reg clk, clr, up, down, ld ; reg [7:0] inp ; wire [7:0] cnt ; wire tc ; // Instantiate the counter cnt8bit uut(cnt, tc, up, down, clr, ld, clk, inp) ; // Generate the clock initial begin $dumpfile("./cnt8bit.dmp") ; $dumpvars(1, cnt8bit_tb) ; clk = 1'b0 ; forever #10 clk = ~clk ; end // Test the counter initial fork #0 begin clr = 1'b1 ; up = 1'b0; down = 1'b0 ; ld = 1'b0 ; inp = 8'd254 ; end #15 begin clr = 1’b0 ; ld = 1'b1; end #25 begin ld = 1'b0 ; up = 1'b1 ; end #75 begin down = 1'b1 ; up = 1'b0 ; end #125 down = 1'b0 ; #150 $finish ; join endmodule

12. Gate-level description of SR latch // // sr latch // cross-coupled nor gates // module sr_latch(q, s, r) ; output q ; input s, r ; wire qbar ; nor u0(qbar, s, q) ; nor u1(q, r, qbar) ; endmodule

13. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit (Rabaey Text, Chapter 6)

14. Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are dual logic networks

15. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

16. PMOS Transistors in Series/Parallel Connection

17. Complementary CMOS Logic Style

18. Example Gate: NAND

19. Example Gate: NOR

20. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C

21. Constructing a Complex Gate

22. Switch-level descriptions of AND and OR gates // Switch-level OR gate module my_or(z, x, y) ; output z ; input x, y ; wire n1, n2 ; supply1 vdd ; supply0 gnd ; // d s g pmos m1(n1, vdd, x) ; pmos m2(n2, n1, y) ; pmos m3(z, vdd, n2) ; nmos m4(n2, gnd, x) ; nmos m5(n2, gnd, y) ; nmos m6(z, gnd, n2) ; endmodule // Switch-level AND gate module my_and(z, x, y) ; output z ; input x, y ; wire n1, n2 ; supply1 vdd ; supply0 gnd ; // d s g pmos m1(n2, vdd, x) ; pmos m2(n2, vdd, y) ; pmos m5(z, vdd, n2) ; nmos m3(n2, n1, x) ; nmos m4(n1, gnd, y) ; nmos m6(z, gnd, n2) ; endmodule

23. Testing my_and and my_or // Test bench for AND and OR gate module test_and_or ; wire z_and, z_or ; reg x, y ; my_and u0(z_and, x, y) ; my_or u1(z_or, x, y) ; initial fork {x, y} = 2'd0 ; #20 {x, y} = 2'd1 ; #30 {x, y} = 2'd2 ; #40 {x, y} = 2'd3 ; join initial begin $monitor($time, " input is %b z_and is %b z_or is %b", {x, y}, z_and, z_or) ; end endmodule