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VGA-RAM

VGA-RAM. Discussion D10.5 3/27/2007-B. VGA - RAM. VGA - RAM. Address at ( x , y ). Pixel 0 1 2 3. signal x,y: std_logic_vector(16 downto 0):. y(11 downto 0) & “00000”. y(9 downto 0) & “0000000”. +. +. addr. “00” & x(14 downto 0). Brian’s RAM Controller.

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VGA-RAM

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  1. VGA-RAM Discussion D10.5 3/27/2007-B

  2. VGA - RAM

  3. VGA - RAM Address at (x,y) Pixel 0 1 2 3

  4. signal x,y: std_logic_vector(16 downto 0): y(11 downto 0) & “00000” y(9 downto 0) & “0000000” + + addr “00” & x(14 downto 0)

  5. Brian’s RAM Controller

  6. ram_ctrl

  7. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Ram_Ctrl.vhd -- Created by Brian Carpenter 03 Dec 2005 -- This device will hook up to the memory and service -- 2 devices in 1 25Mhz clock cycle -- Connect mclk to 50Mhz, clk to 25Mhz -- NOTE: WE is active high entity ram_ctrl is Port ( mclk: in std_logic; clk: in std_logic; clr: in std_logic; ram_ctrl

  8. ram_ctrl Addr0 : in std_logic_vector(18 downto 0); Din0 : in std_logic_vector(15 downto 0); Dout0 : out std_logic_vector(15 downto 0); we0 : in std_logic; Addr1 : in std_logic_vector(18 downto 0); Din1 : in std_logic_vector(15 downto 0); Dout1 : out std_logic_vector(15 downto 0); we1 : in std_logic;

  9. ram_ctrl A : out STD_LOGIC_VECTOR(17 downto 0); IO10 : inout STD_LOGIC_VECTOR(15 downto 0); IO11 : inout STD_LOGIC_VECTOR(15 downto 0); CE1 : out STD_LOGIC; UB1 : out STD_LOGIC; LB1 : out STD_LOGIC; CE2 : out STD_LOGIC; UB2 : out STD_LOGIC; LB2 : out STD_LOGIC; WE : out STD_LOGIC; OE : out STD_LOGIC ); end ram_ctrl;

  10. ram_ctrl architecture ram_ctrl_arch of ram_ctrl is signal ram_data : std_logic_vector(15 downto 0); signal ram_addr : std_logic_vector(18 downto 0); signal oe_out, we_out : std_logic; begin -- Combinational process to setup the outputs comb: process(mclk,clk,Addr0,Din0,we0,Addr1,Din1,we1) begin -- Initialize signals to prevent unwanted latches ram_data <= (others => '0'); ram_addr <= (others => '0'); oe_out <= '1'; we_out <= '1';

  11. -- Switch between devices using the clk as a select line if (clk = '1') then -- select device 0 ram_data <= Din0; ram_addr <= Addr0; oe_out <= we0; else -- select device 1 ram_data <= Din1; ram_addr <= Addr1; oe_out <= we1; end if; ram_ctrl

  12. ram_ctrl -- enable the we only when mclk is low if (mclk = '0') then -- enable the we if (clk = '1') then -- select device 0 we_out <= not we0; else -- select device 1 we_out <= not we1; end if; end if; end process comb;

  13. -- Latch the value for device 0, as it is handled first seq: process(clk,clr,ram_addr,IO10,IO11) begin if (clr = '1') then Dout0 <= (others => '0'); elsif (falling_edge(clk)) then if ram_addr(18) = '0' then -- use IO10 Dout0 <= IO10; else Dout0 <= IO11; end if; end if; end process; ram_ctrl

  14. -- Don't latch device 1's output Dout1 <= IO10 when ram_addr(18) = '0' else IO11; -- Enable only 1 chip CE1 <= ram_addr(18); CE2 <= not ram_addr(18); -- Determine which chips gets the data, use a tristate buffer IO10 <= ram_data when oe_out = '1' else "ZZZZZZZZZZZZZZZZ"; IO11 <= ram_data when oe_out = '1' else "ZZZZZZZZZZZZZZZZ"; ram_ctrl

  15. -- Outputs that drive both chips OE <= oe_out; WE <= we_out; A <= ram_addr(17 downto 0); -- Constant outputs UB1 <= '0'; LB1 <= '0'; UB2 <= '0'; LB2 <= '0'; end ram_ctrl_arch; ram_ctrl

  16. Refresh the video ram ram_ctrl

  17. from Dout1 vga_ram process(vidon, hc) begin red <= '0'; green <= '0'; blue <= '0'; if vidon = '1' then red <= pixel(2); green <= pixel(1); blue <= pixel(0); end if; end process;

  18. vga_ctrl

  19. dreg1 : reg generic map( N => 16 ) port map( d => data1, load => d1ld, clr => clr, clk => clk, q => px1 ); dreg2 : reg generic map( N => 16 ) port map( d => data1, load => d2ld, clr => clr, clk => clk, q => px2 );

  20. mux1 : mux8g generic map( N => 4 ) port map( a => px1(15 downto 12), b => px1(11 downto 8), c => px1(7 downto 4), d => px1(3 downto 0), e => px2(15 downto 12), f => px2(11 downto 8), g => px2(7 downto 4), h => px2(3 downto 0), sel => pmsel, y => pixel );

  21. U3 : vga_ctrl port map( clk => clk, clr => clr, vidon => vidon, d1ld => d1ld, d2ld => d2ld, addr1 => addr1, pmsel => pmsel );

  22. ad1: process(clk, clr, present_state) variable ram_addr: std_logic_vector(18 downto 0); begin if clr = '1' then ram_addr := "0000000000000000000"; elsif clk'event and clk = '1' then if present_state = s1 or present_state = s5 then ram_addr := ram_addr + 1; end if; if ram_addr = ("001" & X"2C00") then ram_addr := "0000000000000000000"; end if; end if; addr1 <= ram_addr; end process;

  23. Clear Screen

  24. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clrscn is Port ( clk : in std_logic; clr : in std_logic; go : in std_logic; done : out std_logic; wec : out std_logic; addrc : out std_logic_vector(18 downto 0); datac : out std_logic_vector(15 downto 0) ); end clrscn;

  25. architecture clrscn of clrscn is type state_type is (start, clear, wtngo); signal state: state_type; signal addr_count: STD_LOGIC_VECTOR (18 downto 0); constant addr_size: STD_LOGIC_VECTOR (18 downto 0) := ("001" & X"2C00"); --76,800 begin datac <= X"0000"; sreg: process(clk, clr) begin if clr = '1' then state <= start; addr_count <= "0000000000000000000"; wec <= '0'; done <= '1';

  26. elsif clk'event and clk = '1' then case state is when start => addr_count <= "0000000000000000000"; if go = '1' then wec <= '1'; done <= '0'; state <= clear; else state <= start; end if; when clear => if addr_count >= addr_size then addr_count <= "0000000000000000000"; state <= wtngo; done <= '1'; wec <= '0'; else addr_count <= addr_count + 1; wec <= '1'; state <= clear; -- stay in clear end if;

  27. when wtngo => if go = '1' then state <= wtngo; else state <= start; end if; end case; end if; end process; addrc <= addr_count; end clrscn;

  28. Plot dot

  29. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity plot is Port ( clk : in std_logic; clr : in std_logic; go : in std_logic; x, y : in std_logic_vector(9 downto 0); data_in : in std_logic_vector(15 downto 0); color : in std_logic_vector(2 downto 0); done : out std_logic; wep : out std_logic; addrp : out std_logic_vector(18 downto 0); datap : out std_logic_vector(15 downto 0) ); end plot;

  30. architecture plot of plot is type state_type is (start, addrout, read, setpix, write, wtngo); signal state: state_type; signal ram_addr1, ram_addr2: STD_LOGIC_VECTOR (18 downto 0); signal data: STD_LOGIC_VECTOR (15 downto 0); signal px: STD_LOGIC_VECTOR (1 downto 0); signal pixel: STD_LOGIC_VECTOR (3 downto 0); constant addr_size: STD_LOGIC_VECTOR (18 downto 0) := ("001" & X"2C00"); --76,800 begin pixel <= '0' & color; process(x, y) begin ram_addr1 <= ("00" & y & "0000000") + ("0000" & y & "00000"); -- y*(128+32) ram_addr2 <= ram_addr1 + ("00000000000" & x(9 downto 2)); -- y*160+x/4 px <= x(1 downto 0); end process;

  31. sreg: process(clk, clr) begin if clr = '1' then state <= start; addrp <= "0000000000000000000"; wep <= '0'; done <= ‘1'; elsif clk'event and clk = '1' then case state is when start => wep <= '0'; if go = '1' then state <= addrout; done <= ‘1'; else state <= start; end if;

  32. when addrout => state <= read; addrp <= ram_addr2; wep <= '0'; when read => state <= setpix; data <= data_in; wep <= '0'; when setpix => state <= write; wep <= '0'; case px is when "00" => data(15 downto 12) <= pixel; when "01" => data(11 downto 8) <= pixel; when "10" => data(7 downto 4) <= pixel; when "11" => data(3 downto 0) <= pixel; when others => null; end case;

  33. when write => state <= wtngo; datap <= data; done <= '1'; wep <= '1'; when wtngo => wep <= '0'; if go = '1' then state <= wtngo; else state <= start; end if; whenothers => null; end case; end if; end process; end plot;

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