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Advanced Fault-Tolerant Processor Mesh Architecture

Explore the special features of the ISA, including fast local communication, aggregate functions, integer arithmetic, and more. This architecture offers fault tolerance through reconfiguration and majority voting for mission-critical tasks, ensuring high reliability. Utilizes a torus structure with distributed shared memory, prefetch capabilities, and dynamic task allocation for optimal performance. Enhance your understanding of processor arrays, fault patterns, and survival probabilities in complex computing environments.

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Advanced Fault-Tolerant Processor Mesh Architecture

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  1. M. Kunde H.W. Lang M. Schimmler H. Schmeck H. Schröder • Special features of the ISA: • fast local communication • aggregate functions with • constant period • fast integer arithmetic RAM NORTH RAM WEST Controller program memory host computer bus ISA Interface processors Architecture of Systola 1024

  2. 1 M bit 1 M bit memory control PIPS architecture • Torus 32x32 • off-the-shelf SRAM as distributed shared memory with prefetch

  3. reconfigurable mesh = mesh + interior connections low cost diameter 1 !! 15 positions

  4. CAN shadow-processors majority voting Fault tolerance through reconfiguration

  5. majority voting Mission-critical tasks can be taken over by any processor PS(k)= probability of survival under the assumption that k processors fail. For the “shadow system” with 16 = 8x2 processors: PS(1)=1, PS(2)=0.93, PS(4)=0.6, PS(6)=0.22, PS(8)=0.02

  6. instrument processor “atomic fault pattern” A simple solution with high fault tolerance (torus) Every fault pattern, that does not contain a 2x2 array of faulty PEs survives. PS(7)=0.7

  7. on the “other side” processor task Torus: 16 task 32 processors PS(5)=1 How about 32 tasks and 16 processors ??

  8. majority voting 6-neighborhood torus PS(5)=1

  9. Distributed shared memory ? Migration of contents ? Memory/voting/error-correction Memory/voting/error-correction Memory/voting/error-correction Memory/controller/error-correction

  10. Assumption: The processors are identical and have at least twice the required capacity. Other devices do not fail. N I W P E S 4x4 torus = 4D hypercube

  11. If less then 9 processors fail, no processor needs to take more than 2 tasks. The processors time-share between the tasks. PS(10)=1 ?

  12. N I 3 3 W 2 2 P E 1 3 3 S 2 2 3 3 PS(7)=1 ?? 1-processor/1-task ?? spares - torus ?? control of switches ??

  13. PS N I 1 W P E S 8 16 # faults Number of switches: 2, 4, 6, 30 Wire area: 0, 2.8, 3.8, 4

  14. Load balancing dynamic allocation of tasks

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