FPGA Configuration Interfaces

1. FPGA Configuration Interfaces

2. After completing this presentation, you will able to: • Describe the purpose of each of the FPGA configuration pins • Explain the differences between the available configuration schemes • Choose an appropriate FPGA configuration scheme for your application • Identify how to connect multiple FPGAs into a configuration daisy chain

3. Configuration Data Source FPGA Control Logic (Optional) Introduction • What is configuration? • Process for loading configuration data into the FPGA

4. Introduction • When does configuration happen? • On power up • On demand • Why do FPGAs need to be configured? • FPGA configuration memory is volatile • Configuration data is stored in a PROM or other external data source • What do you need to know about FPGA configuration? • What happens during configuration • How to set up various configuration modes and daisy chains

5. FPGA Configuration Methods Xilinx PROMs: Slave/Master Serial Slave/Master SelectMAP Xilinx Cables: JTAG Slave Serial Slave SelectMAP FPGA Microprocessor: JTAG Slave Serial Slave SelectMAP Commodity Flash: Slave SelectMAP SPI* BPI* *SPI and BPI support is available in Spartan™-3E, -3A, -3A DSP, -6, Virtex™-5, and -6

6. Configuration time for different Configuration interfaces • Virtex-4 XC4VLX15 with bitstream size of 4,765,568 • The smallest Virtex -4 LX

7. Reconfiguration time for Xilinx Virtex-4 devices using SlectMap32 Slaver Serial mode

8. FPGA Configuration Process • To understand the configuration process, you need to know about • Configuration modes • Configuration pins

9. Configuration Pins • Specific pins on the FPGA are used during configuration • Some pins act differently depending on the configuration mode • Example: CCLK is an output in some modes and an input in others • Some pins are only used in specific configuration modes

10. Configuration Pins • Mode pins • Input pin(s) that select which configuration mode is being used • PROGRAM_B • Input that initiates configuration • Active Low • CCLK (configuration clock) • Input or output (depending on configuration mode) • Frequency up to 100 MHz (dependent on the FPGA, see configuration user guide) • INIT_B • Open-drain bi-directional pin • Error and power stabilization flag • Active Low • DONE • Open-drain bi-directional pin • Indicates completion of configuration process

11. Configuration Pins • DIN • Serial input for configuration data • DOUT • Output to the next device in a daisy chain • Used in daisy chains only • Other pins are used for specific configuration modes • Note that some configuration pins are dual purpose • They become user I/O after configuration is complete

12. Many Configuration Modes • Serial (one data line) • JTAG • Primarily for debugging and prototyping, recommended for all applications, external control logic provided by download cable and JTAG chain • Master Serial • Control logic is a part of the FPGA, uses serial Flash (such as Platform Flash PROM) • Slave Serial • External control logic is necessary, built by user • SPI (Serial Peripheral Interface) • Control logic in FPGA, uses an industry-standard SPI Flash PROM, usually used in embedded applications • Parallel (8-bit , 16-bit or 32-bit data lines) • Master SelectMAP • Control logic is a part of the FPGA, uses parallel Flash (such as Platform Flash) • Slave SelectMAP • External control logic necessary, built by user • BPI (Byte-Wide Peripheral Interface) • Control logic is a part of the FPGA, uses an industry-standard NOR Flash, usually used in embedded applications

13. JTAG Configuration Mode • TCK is driven by your Xilinx programming cable • The bitstream is stored on your computer and is downloaded via the ISE™ software iMPACT utility and a Xilinx programming cable • Primarily used for debugging • Control signals are in parallel • Unique programs are shifted into the appropriate device TCK ISE (iMPACT) + Cable FPGA FPGA FPGA TDI TDO TDO TMS TDO

14. Master Serial Configuration Mode • FPGA provides all control logic • All mode pins are tied Low • Slave serial mode requires external control logic • Master Serial mode • FPGA drives configuration clock (CCLK) as an output • Data is loaded 1 bit per CCLK • Used when data is stored in a serial PROM (usually a Xilinx Platform Flash PROM) • Slowest configuration mode, but the easiest to debug Xilinx Platform Flash PROM CCLK FPGA Data

15. Slave Serial Configuration Mode • External control logic required to generate CCLK • Microprocessor or microcontroller • Xilinx serial download cable • Another FPGA • Data is loaded 1 bit per CCLK • All mode pins are tied High Serial Data FPGA Data CCLK Control Logic

16. Master SelectMAP Mode • FPGA provides all control logic • Sometimes called Master Parallel mode • FPGA drives address bus • Data is loaded 1 byte per address • Data internally serialized • FPGA generates 8 CCLKs per byte • Usually targets Xilinx Platform Flash XL or another vendors Platform Flash PROM • The Xilinx Platform Flash XL also works in BPI mode and is a popular memory resource for Virtex-5 and Virtex-6 • This enable faster configuration times CCLK Byte-Wide Data Source FPGA Data

17. Slave SelectMAP Mode • External control logic required (microprocessor or microcontroller, for example) • Data presented 1 byte at a time • Virtex-5 and Virtex-6 support x8, x16, and x32 • Spartan-6 supports x8 and x16 • Ready/Busy handshaking • Asynchronous Peripheral • Control logic provides a Write strobe • Triggers FPGA to generate 8 CCLK pulses • Synchronous Peripheral • CCLK provided by control logic (8 pulses per data byte) • Can target Xilinx Platform Flash XL • This would not require external control logic Byte-Wide Data FPGA Data Ready/Busy Control Signals Control Logic

18. Serial Peripheral Interface (SPI) Mode • FPGA configures itself from an attached industry-standard SPI serial Flash PROM • FPGA issues a command to Flash and it responds with the data • Can be used in multi-boot applications where multiple bitstreams can be loaded by the FPGA • Data is loaded 1 bit per CCLK • There are no standards for the commands • Commands are vendor specific • Vendor Select (VS) pins tell the FPGA which commands to issue SPI Flash PROM CCLK FPGA Data Command

19. Byte-Wide Peripheral Interface (BPI) Mode • FPGA issues an address to a BPI Flash, which responds with the data • Uses standard parallel NOR Flash interface • No clock is needed because the FPGA contains the control logic • Usually used in embedded applications • Flash is easily used as addressable memory with address and data buses • Supported for Virtex™-5, Virtex-6, Spartan™-3E, and Spartan-6 FPGAs • Xilinx Platform Flash XL is a 128 Mb parallel NOR and works in BPI and SelectMAP modes BPI NOR Flash FPGA Data Addr[26:0]

20. Loading a Partial Bit File External Reconfiguration via uP Internal Reconfiguration configuration memory RM A1 config. full configuration RM A2 config. RM A3 config. Off-chip memory or System ACE ICAP uP FPGA Self-reconfiguring FPGA uP PRR A PRR A JTAG port

21. Internal Configuration Access Port (ICAP) • ICAP is the internal configuration access port for Virtex-II and later-generation Virtex devices • It is a functional subset of SelectMap and is accessible internally via a user design • It allows the user design to control device reconfiguration at run-time • It becomes available after initial (externally controlled) configuration is complete

22. SelectMAP and ICAP ICAP SelectMAP D[0:7/31] I[0:7/31] O[0:7/31] DONE INIT BUSY BUSY CS CE WRITE WRITE PROGRAM CCLCK CCLCK M2 M1 M0

23. File Generation • BitGen • Used to generate Xilinx FPGA bitstreams (.BIT) for configuration • Requires a native circuit design (.NCD), which is made after place and route has been successfully completed • NCD defines the internal logic and interconnections for your FPGA design • iMPACT • GUI tool used to generate PROM Files • Used to configure FPGAs in-system, directly from a host-computer with a Xilinx download cable

24. File Generation • PROMGen • Used to generate PROM Files • Formats a bitstream file (.BIT) into a PROM format file • Supports MCS-86 (Intel), EXORMAX (Motorola), and TEKHEX (Tektronix) • Can also generate a binary or hexadecimal file

25. Prototyping Solutions • Platform Cable USB • Low-cost JTAG/Slave Serial ISP cable connects to USB port • Configures Xilinx FPGAs • Programs Xilinx CPLDs and PROMs • Parallel Cable IV • Low-cost JTAG/SlaveSerial cable connects to PC parallel port • Configures Xilinx FPGAs • Programs Xilinx CPLDs and PROMs • Platform Cable USB II • Low-cost JTAG/Slave Serial ISP cable connects to USB port • Configures Xilinx FPGAs • Programs Xilinx CPLDs and PROMs • Programs SPI flash memory devices • Note: Xilinx hardware solutions are not recommended for production programming

26. Configuration Sequence • Steps are the same for all devices and modes • Device Power-Up • This timing diagram shows the first 3 steps of configuration • Check that your system powers-up the FPGA quickly enough • INIT_B is a bi-directional open-drain pin (external pull-up is required)

27. Configuration Sequence • Start-Up • The startup sequence is controlled by an 8-phase sequential state machine • The startup sequencer performs the following tasks (user selectable) • Wait for DCMs to Lock (optional) • Wait for DCI to Match (optional) • Negate Global 3-state (GTS) (which activates I/O) • Release DONE pin (open-drain output requiring an external pull-up) • Assert Global Write Enable (GWE) (allows RAMs and FFs to change state) • Assert End of Startup (EOS) • Note that last 4 steps are default

28. What is a Daisy Chain? • Multiple FPGAs connected in series for configuration • Allows configuration of many devices from a single data source • Minimizes the board traces necessary • In our example, the first device in this serial daisy chain can be in any configuration mode, but we chose the Master Serial mode • All other devices must be in Slave Serial mode • Note that additional configuration modes support daisy chains

29. Creating a Serial Daisy Chain (Virtex-6) • Connect all PROGRAM and CCLK pins together • Connect each DOUT to the DIN of the next device • Connecting INIT and DONE pins is recommended • First device is in Master Serial (000), second is in Slave Serial (111)

30. Creating a Daisy Chain • Connect PROGRAM pins • Required so that all FPGAs will all reprogram together • Connect CCLK pins • Required so that all FPGAs are synchronized with each other and with the data stream • Connect each DOUT to the DIN of the next device • Required to allow each FPGA to receive the data stream • Connect INIT pins • Creating a single error flag is recommended • Connect DONE pins • Creating a single status flag is recommended • Connect DONE to the CE input of your PROM

31. How Does a Daisy Chain Work? • A synchronization word is passed to each device in the chain • The first FPGA in the chain is configured first • Keeps DOUT High until its configuration memory is full • Then data is passed to the next device in the chain • The startup sequence occurs after all devices are configured

32. Questions ?

33. Question • Should my FPGA load its configuration data from external memory or should a processor or microcontroller download the configuration data? • The benefit of slave modes is that the bitstream can be stored pretty much anywhere in your hardware system • Control logic can allow for in-system delivery of FPGA design updates • Additional components will have to be purchased • Debugging your custom control circuitry can be challenging • Master configuration schemes already have the control logic built inside of the FPGA, so debugging is minimal • Always include a JTAG configuration path for easy debugging

34. Question • Should my system use a single FPGA or multiple FPGAs? • Most applications use a single FPGA • But some applications require multiple FPGAs for increased logic density or I/O • Multiple FPGA systems should have a single configuration data source and use a daisy chain • This reduces cost and simplifies programming and logistics • All of the configuration schemes support daisy chains

35. Question • Which is the simplest configuration scheme to debug? • Master Serial, BPI, and SPI modes are probably the easiest to use • Using any master configuration mode will be the easy to debug because you did not have to build the external control logic • Master modes use the fewest pins • Verses parallel modes which are the fastest, but have the most pins to debug

36. Question • Should I choose the lowest-cost configuration solution? • Do you already have a spare, non-volatile memory component in your system? • The bitstream can be stored in system memory, on a hard drive, or downloaded remotely over a network connection • Is there a way to consolidate the non-volatile memory required in your application? • Can the bitstream of your FPGA be stored with any processor code for your application (such as an embedded application)? • Can you use the SPI or BPI configuration schemes? • Because these devices have common footprints and multiple suppliers, they may have lower pricing due to highly competitive markets

37. Question • Is the fastest possible configuration time the more important consideration? • Parallel configuration schemes are inherently faster than serial modes • Configuring a single FPGA is inherently faster than configuring multiple FPGAs in a daisy chain • In master modes, the configuration clock frequency of the FPGA can be increased using the ConfigRate bitstream option • The maximum speed depends on the read specifications for the attached non-volatile memory. • A faster memory can allow for faster configuration • The clock made by the FPGA varies by process. The fastest configuration rate depends on this clock, so check your data sheet • If an external clock exists in your application, you can configure in slave mode while using attached non-volatile memory

38. Question • Will the FPGA be loaded with a single configuration image or multiple images? • Most applications use one image and the FPGA is configured when power is turned on • Some applications re-load the FPGA multiple times, while the system is operating, with different bitstreams for different functions (called MultiBoot) • For example, the FPGA can be loaded with one bitstream to implement a power on self-test, followed by a second with the final application • In test equipment applications, the FPGA is loaded with different bitstreams to execute hardware-assisted tests. With this method, one small FPGA can implement the equivalent functionality of a larger ASIC or FPGA • The JTAG and slave modes easily support reloading the FPGA with multiple images • However, reloading multiple images is also possible in Master schemes with the newest FPGAs using the MultiBoot feature

39. Question • What I/O voltages are required in the end application? • The chosen FPGA configuration mode places some constraints on the FPGA application—specifically the I/O voltage allowed on the configuration banks of the FPGA • SPI and BPI modes leverage third-party Flash memory components that are usually 3.3V-only devices • This requires that the I/O voltage on the banks attached to the memory also be 3.3V • If a voltage other than 3.3V is required, specifically Virtex-6, consider using a Xilinx Platform Flash PROM • Numonyx, Spansion, and Winbond are considering producing a flash memory that is compatible with Virtex-6

40. Questions • Should the FPGAs I/O pins be pulled High via resistors during configuration? • Some of the FPGA pins used during configuration have dedicated pull-up resistors during configuration • The majority of user I/O pins have optional pull-up resistors • Why enable the pull-up resistors during configuration? • Floating signal levels are a problem in CMOS logic systems • The internal pull-up resistors generate a logic High level on each pin • Similarly, an individual pin can be pull-down using an appropriately-sized external pull-down resistor • Why disable pull-up resistors during configuration? • In hot-swap or hot-insertion applications, the pull-up resistors provide a potential current path to the I/O power rail • Turning off the pull-up resistors disables this potential path • However, external pull-up or pull-down resistors are then required on each individual I/O pin

41. Question • Does the application target a specific FPGA density or should it support migrating to other FPGA densities in the same package footprint? • The package footprint and pinouts for some Xilinx families are designed to allow migration among different densities within a specific family • For example, three different Spartan™-3E FPGAs support the identical package footprint when using the 320-ball fine-pitch ball grid array package (FG320) • The smallest of devices, the XC3S500E, requires approximately 2.2 Mbits for configuration. The largest of these devices, the XC3S1600E, requires 5.7 Mbits for configuration • To support design migration among device densities, allow sufficient configuration memory to cover the largest device in the targeted package (remember to include the size of any software)