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MSI Directory Protocol Example

Explore memory management in directory protocol example with structural dependencies, races, optimizations, and challenges in multi-core systems. Learn about serialization of requests and solutions.

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MSI Directory Protocol Example

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  1. MSI Directory Protocol Example Main Memory Mem[0xA] = 3 3 Directory ShReq 0xA ShResp 0xA, data=3 2 4 Cache 1 Cache 0 Cache 2 Core 1 Core 0 Core 2 LD 0xA 1 http://www.csg.csail.mit.edu/6.823

  2. MSI Directory Protocol Example Main Memory Mem[0xA] = 3 3 Directory ShReq 0xA ShResp 0xA, data=3 2 4 Cache 1 Cache 0 Cache 2 Core 1 Core 0 Core 2 LD 0xA 1 http://www.csg.csail.mit.edu/6.823

  3. MSI Directory Protocol Example Main Memory Mem[0xA] = 3 5 Directory ExResp 0xA data = 3 InvReq 0xA InvReq 0xA 3 ExReq 0xA 3 2 6 InvResp 0xA InvResp 0xA 4 4 Cache 1 Cache 0 Cache 2 Core 1 Core 0 Core 2 ST 0xA 1 http://www.csg.csail.mit.edu/6.823

  4. MSI Directory Protocol Example Main Memory Mem[0xA] = 5 Mem[0xB] = 10 6 3 Directory WbResp 0xA 4 WbReq 0xA, data=5 ExResp 0xB, data=10 ExReq 0xB 2 5 7 Cache 1 Cache 0 Cache 2 Core 1 Core 0 Core 2 ST 0xB 1 Why are 0xA’s wb and 0xB’s req serialized? Structural dependence Possible solutions? Buffer outside of cache to hold write data http://www.csg.csail.mit.edu/6.823

  5. Directory-Induced Invalidations • To retain inclusion, must invalidate all sharers of an entry before reusing it for another address • Example: 2-way set-associative sparse directory Mem[0xB] = 5 5 Main Memory ShReq 0xB ShResp 0xB,data=5 2 6 Directory InvReq 0xA 3 InvResp 0xA 4 Cache 1 Cache 0 Cache 2 Core 1 Core 0 Core 2 LD 0xB 1 How many entries should the directory have? http://www.csg.csail.mit.edu/6.823

  6. Protocol Races • Directory serializes multiple requests for the same address • Same-address requests are queued or NACKed and retried • But races still exist due to conflicting requests • Example: Upgrade race Caches 0 and 1 issue simultaneous ExReqs InvReq 0xA 3 ExReq 0xA ExReq 0xA 2 2’ Main Memory Directory starts serving cache 0’s ExReq, queues cache 1’s Directory ReqQ 1, ExReq 0xA Cache 1 expected ExResp, but got InvReq! Cache 0 Cache 1 ST 0xA ST 0xA 1’ 1 Cache 1 should transition from S->M to I->M and send InvResp Core 0 Core 1 http://www.csg.csail.mit.edu/6.823

  7. Optimization: 3-hop Protocols • Reduce latency by having a neighbor cache forward data to requester Main Memory ExReq 0xA Directory 2 ExFwd 0xA, req=2 3 ExAck 0xA 4 Cache 1 Cache 0 Cache 2 Core 1 Core 0 Core 2 ST 0xA ExResp 0xA,data=3 1 3 http://www.csg.csail.mit.edu/6.823

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