SiFive - Promoting RISC-V Technology Innovation and Development

1. SiFive Promotes RISC-V Technology Innovation and Development SiFive推动RISC-V技术创新与发展 周杰 赛昉科技销售总监 jie.zhou@sifive.com Sept.2019

2. What is RISC-V? A license-free, royalty-free High-quality, Suitable for all types of computing system, RISC ISA specification, Originally from UC Berkeley RISC-I RISC-II RISC-III (aka SOAR) RISC-IV (aka SPUR) RISC-V (Raven-1, 28nm FDSOI, 2011) 第一代 第二代

3. Foundation David Patterson Google杰出工程师 &SiFive 技术顾问 Andrew Waterman SiFive 联合创始人 & 首席工程师 Yunsup Lee SiFive 联合创始人 &CTO KrsteAsanovic SiFive 联合创始人 & 首席架构师 We invented RISC‑V SiFive’s founders are the same UC Berkeley professor and PhDs who invented and have been leading the commercial implementation of the RISC‑V Instruction Set Architecture (ISA) since 2010

4. RISC-V发展史及其标志性事件 Privileged Arch, v1.10 RISC-V Foundation Incorporated 1st Rocket tapeout, EOS14 45nm Hot Chips 2014 User ISA v2.0 IMAFD UserISA v1.0, Raven-1 tapeout (28nm) RVC MS thesis 1st China 5City Tour 1st Commercial Linux SoC Commercial Softcores Qualcomm to RISC-V SiFiveIncorporated 1st Commercial SoC 1st RISC-V Summit NVIDIA to RISC-V RedHat to RISC-V WDC to RISC-V 1st Workshop We are Here RISC-V ISA project begins First Linux Port 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

5. What’s Different about RISC-V? • Simple • Far smaller than other commercial ISAs • Stable • Base and standard extensions are frozen • Additions via optional extensions, not new versions • Clean-slate design • Clear separation between user and privileged ISA • Avoids µarchitecture or technology-dependent features • Community designed • Developed with leading industry/academic experts and software developers • Modular ISA designed for extensibility/specialization • Small standard base ISA, with multiple standard extensions • Sparse and variable-length instruction encoding for vast opcode space

6. Why SiFive? SiFive team has 8 years of experience taping out RISC-V silicon.... Freedom Everywhere Base Platform • Leaders in RISC-V • Inventors of RISC-V • Major contribution inmostallfoundation working group • Leaders in RISC-V standardization • Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors • Very easy to customize • Silicon-proven and our licensees are shipping Raven-3 Raven-1 Started RISC-V Project Raven-2 Raven-3.5 Apr Aug Feb Jul Sep Mar May Nov May Jul Nov Aug Oct 2011 2012 2013 2014 2015 2017 2016 2010 Started Development of RISC-V Core Generator EOS22 Foundation EOS18 EOS14 Freedom Unleashed Base Platform EOS20 EOS16

7. Why SiFive? • Leaders in RISC-V • Inventors of RISC-V • Major contribution inmostallfoundation working group • Leaders in RISC-V standardization • Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors • Very easy to customize • Silicon-proven and our licensees are shipping

8. Why SiFive? • Leaders in RISC-V • Inventors of RISC-V • Major contribution inmostallfoundation working group • Leaders in RISC-V standardization • Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors • Very easy to customize • Silicon-proven and our licensees are shipping

9. Embedding Intelligence from the Edge to the Cloud 64-bit Application Processors Intelligent Cloud 64-bit Embedded Processors Intelligent Edge 32-bit Embedded Processors

10. SiFive RISC-V Core IP Product Series • Coherency Manager for cores configured with Data Caches • SiFive Insight • Architectural Clock Gating • Run/Halt Debug with configurable number of breakpoints and support for JTAG and cJTAG • Configurable number of Hardware Performance Counters • Optional Instruction Trace • Optional ECC Features Common to all SiFive IP Products • Optional RISC-V Standard Extensions: M, A, C, F, and D • Configurable hardware multiplication performance • Configurable number, type, and width of Ports • Configurable Platform Level Interrupt Controller (PLIC) Production Ready Features High performance 64-bit Application Cores Industry leading 32-bit and 64-bit Embedded Cores • Coherent Multi-Core • Data Cache or DTIM • Optional I$ and optional ITIM • Singe and Double Precision FPU • Optional L2 Cache • Configurable Branch Prediction structures • Optional User Mode • Coherent, Heterogeneous Multi-Core • Data Cache or DTIM • Optional I$ and optional ITIM • Singe and Double Precision FPU • Optional L2 Cache • Configurable Branch Prediction structures Optimized High-Performance High Performance Embedded • Coherent Multi-Core • Data Cache or DTIM • Reconfigurable I$/ITIM • Singe and Double Precision FPU • Optional L2 Cache • Configurable Branch Prediction structures • Optional User Mode • Coherent, Heterogeneous Multi-Core • Data Cache or DTIM • Reconfigurable I$/ITIM • Singe and Double Precision FPU • Optional L2 Cache • Configurable Branch Prediction structures Multi-Core RISC-V Linux Small, Efficient, Performance • Optional Harvard Pipeline • CLIC with IRQ Vectoring • Configurable TIMs • Single Precision FPU • Optional User Mode SiFive’s Most Efficient Series

11. The Smallest, Most Efficient RISC-V MCU Family E2 Series Features • E2 Series core architectural overview • RV32(E)IMAFDCVN capable core • 2-3 stage, optional, Harvard Pipeline • Efficient memory accesses • Ability to add multiple outbound Ports • Optional Tightly Integrated Memory (TIM) and Optional Instruction Cache • First RISC-V core with support for the RISC-V Core Local Interrupt Controller (CLIC) • Provides hardware interrupt prioritization and nesting • Only 6 cycles to execute the first instruction of IRQ • SiFive Custom Instruction Extension (SCIE) • Easily add support for custom instructions

12. SiFive Core IP 3 and 5 series: 32-bit Embedded Processors 64-bit Embedded Processors 64-bit Application Processors The world's most deployed RISC-Vprocessor IP Efficient Performance Coherent, Heterogenous, Multicore Hard Real-time capabilities Configurable Efficient Mature

13. E3/S5 Overview High Performance 32bit and 64bit RISC-V MCUs • Flexible memory architecture • I-Cache can be reconfigured into I-Cache + ITIM • DTIM for fast on Core Complex Data Access (D-Cache option also available) • ECC/Parity Protection • Off Core Complex memory access through Memory, System and Peripheral Ports • Multicore Support • Pre-integrated and verified by SiFive • Supports up to 8+ cores • Fast Interrupts • Supports 16 local and up to 255 global interrupts • E3/S5 with Interrupt Handlers in ITIM can enter an ISR in 10 cycles • Support Vectoring for direct handler entry • Does not require separate VIC • Memory Protection • 8 region physical memory protection • Region locking *E31 w/ AHB Ports, PLIC w/ 127 IRQ, Debug w/ 4 hw breakpoints, CLINT, area does not include RAMs **S51 w/ AXI Ports, PLIC w/ 255 IRQ, Debug w/ 4 hw breakpoints, CLINT, area does not include RAMs ***unknown configuration: https://developer.arm.com/products/processors/cortex-r/cortex-r5

14. SiFive Core IP 7 series: 32-bit Embedded Processors 64-bit Embedded Processors 64-bit Application Processors The highest performance commercial RISC-V processor IP Common Feature sets Hard Real-time capabilities Unprecedented scalability ~60% increase in CoreMarks/MHz* ~40% increase in DMIPS/MHz* 10% increase in Fmax* *Compared to SiFive 5 series

15. SiFive7series Features Scalable throughput provided by 8+1 cores per cluster Enhanced determinism for hard real-time constraints Tightly integrated memory for low latency access Functional safety provided by in-built fault tolerance mechanisms Cache lock capability for mission-critical computing Configurable memory architecture for application specific tuning Extensible design via custom instructions 64-bit addressability for real time latency sensitive applications A single pre-integrated and verified deliverable Mixed-precision arithmetic for efficient compute of ML workloads In-cluster coherent combination of real-time and application processors

16. Linley MPR – “SiFive Raises RISC-V Performance”

17. SiFive RISC-V Standard Core Roadmap Released Std Core Denotes Early Access Standard Core Release Q4’18 Q1’19 Q2’19 Q3’19 Q4’19 Q1’20 8 Series Super Scalar 12 stage pipeline Out of Order U84 High Performance OoO AP 7 Series Dual Issue 8 stage pipeline E, S, U Cores U74 High Performance AP U74-MC Multi-Core AP U77, S77, E77 Vector Unit S76, E76 High-Performance Embedded S76-MC, E76-MC Multi-Core Embedded 5 Series Single Issue 5-6 stage pipeline Multi-Core S and U Cores U54-MC4 U54 S54 U52 No L2$ S51 3 Series Single Issue 5-6 stage pipeline Multi-Core E Cores E31 E34 2 Series Power/Area Optimized 2-3 stage pipeline E and S Cores E24 E27, S27 MCU + Vector Unit E21 E20 S21 64-bit MCU

18. Why SiFive? • Leaders in RISC-V • Inventors of RISC-V • Major contribution inmostallfoundation working group • Leaders in RISC-V standardization • Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors • Very easy to customize - SiFive Core Designer • Silicon-proven and our licensees are shipping

19. SiFive is Your Virtual CPU Team Cloud-based Customize your own RISC-V core Unique for your application Not shared with your competitors Verified, Customized RISC-V IP Product Specific, Unique Requirements SiFive Core Designer uControllers | Embedded | Linux | Multicore Features | Power | Performance | Area Web Interface Verilog RTL From the Inventors of RISC-V

20. NEW IP PARADIGM • Annual subscription allows a customer’s engineers to access SiFive’s entire processor portfolio via a simple web interface • Configuring SiFive’s processor IP is fast and easy • A configured processor is generated in the cloud and the results are delivered to the user’s SiFive dashboard (RTL, SDK, test bench, docs) • Explore Before allows engineers to analyze their configured cores in their system simulations before committing to using them • There is no processor modeling language to learn and no IP configuration tools to install • FPGA bitstreams are provided to allow SW to run on a configured processor SiFive CoreDesigner • RISC-V grants every user the right to modify their processor IP; • SiFive has made it incredibly easy to do so.

21. IP Deliverables SiFive RISC-V Core IP RTL deliverable: • Readable, SiFive verified, Verilog with no restrictions • Delivered Configured and Integrated • Bundled test bench with example tests • Standard Core and Freedom Core Designer deliverables are the same. • SiFive verifies your configuration in-house and delivers Verilog SiFive RISC-V Core IP FPGA deliverable: • Trial Variant FPGA evaluations are bitstreams of a configured core targeting our standard FPGA platforms • Digilent Arty • Xilinx VC707 • Future FPGA platforms (Amazon F1, Microsemi Polar Fire) • Trial Variant FPGA evaluations provide a useful platform for early software development and algorithm benchmarking • Including a useful subsystem with peripherals like UARTs, and GPIOs

22. Software Development

23. SiFive Freedom Studio • Freedom Studio • Eclipse + CDT + GNU MCU Eclipse • Bundled Toolchain and OpenOCD Binaries • Example software for SiFive platforms • Peripheral register viewer • Multicore debug support • QEMU for simulation of SiFive platforms • Write and validate software before having access to silicon or emulation • Debug probe support • OpenOCD probes such as Olimex • SEGGER JLINK • Supports Windows, Mac, Linux

24. Supported Debug Transport Hardware - JTAG Probes SiFive HiFive Unleashed & HiFive1 (FTDI) Olimex ARM-USB-TINY Probe PC (Debug Host) or Digilent Arty FPGA Debug TranslatorOpenOCD Debug TranslatorSEGGER J-Link SiFive HiFive1 revB (J-Link OB) SEGGER J-Link Probe

25. Why SiFive? • Leaders in RISC-V • Inventors of RISC-V • Major contribution inmostallfoundation working group • Leaders in RISC-V standardization • Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors • Very easy to customize - SiFive Core Designer • Silicon-proven and our licensees are shipping

26. Our Approach Has Produced Many World’s Firsts 与微软合作实现了世界首款基于云端设计的芯片量产 世界首款基于RISC-V的SSD控制器 1.5+ GHz U54-MC SiFive CPU 1x E51: 16KB L1I$, 8KB DTIM 支持 ECC 4x U54: 32KB L1I$, 32KB L1D$ 支持 ECC 单、双精度浮点支持基于directory的2MB Banked L2$ 及cache一致性并且支持ECC ChipLink Serialized Chip-to-Chip Coherent TileLink Interconnect DDR3/4, GbE, Peripherals Freedom U540 由台积电28nm工艺制造 “SiFive基于RISC-V的IP只有其它竞品方案1/3的功耗及1/3的面积, 这能给予我们所需的灵活性以优化我们的架构来创造许多突破性的产品。” – Jihyo Lee, FADU CEO OTP GbE E51 U54 U54 U54 U54 DDR L2$

27. AMAZFITSmartWatch2w/ ECG RMB999 E3 core inside AMAZFITBIPWatch RMB299 AMAZFITSmartWatch2w/o ECG RMB799

28. 55 Over50commerciallicenseesworldwide 21 21commerciallicenseesinChina 6ofthetop10semiconductorcompaniesintheworldhavebecomeSiFivecustomers 6/10 120 Over100SiFiveRISC-VIPbasedprojectsinprogress SiFiveUScompletesD-round’sfinancingandQualcommbecomesanewinvestor 65.4M

29. ContactUs sales@sifive-china.com marketing@sifive-china.com recruitment@sifive-china.com • BestinclassinRISC-Vbasedsolutionwithlocalcustomersupport • LeaderinRISC-VecosystemdevelopmenttosupportChinasemiconductorindustry,growingwithopen-sourcecommunity • Pioneerincloud-basedSaaSserviceforcustomASICs. 周 杰 赛昉科技销售总监 15381185012 jie.zhou@sifive.com