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Greatest Common Divisor --- 最大公约数

Greatest Common Divisor --- 最大公约数. 主要内容. 算法描述 电路模块 Verilog 描述 Modesim 仿真结果与结论 综合结果. begin. yes. A=0 orB=0. no. A=0. B=0. yes. no. A>=B. yes. A=A-B. END. no. Swap A B. 算法描述. Q. Q. D. D. >. >. 0. 0. 0. 0. 0. 1. Q. Q. mux. mux. mux. mux. mux. mux.

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Greatest Common Divisor --- 最大公约数

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  1. Greatest Common Divisor ---最大公约数

  2. 主要内容 • 算法描述 • 电路模块 • Verilog描述 • Modesim仿真结果与结论 • 综合结果

  3. begin yes A=0 orB=0 no A=0 B=0 yes no A>=B yes A=A-B END no Swap A B 算法描述

  4. Q Q D D > > 0 0 0 0 0 1 Q Q mux mux mux mux mux mux 1 1 1 0 1 1 B_hold clock 电路模块 load A_hold Compare A< B A[7:0] Y[7:0] A-new Rest_N — A-B B[7:0] B_hold Compare B=0 done

  5. Verilog description1/3 • //description the D_regs of A_hlod and B_hold • always @ (posedge clock) • begin • if(reset) • begin • A_hold<=8'h00; • B_hold<=8'h00; • end • else • if(load) • begin • A_hold<=A; • B_hold<=B; • end • else • if(A_lessthan_B) • begin • A_hold<=B_hold; • B_hold<=A_new; • end • else • begin • A_hold<=A_new; • B_hold<=B_hold; • end • end

  6. Verilog description 2/3 • what is the A_new and A_lessthan_B • always @ (A_hold or B_hold) • begin • if(A_hold<B_hold) • begin • A_lessthan_B=1'b1; • A_new=A_hold; • end • else • begin • A_lessthan_B=1'b0; • A_new=A_hold-B_hold; • end • end

  7. Verilog description 3/3 • //GCD and done • always @ (A_hold or B_hold) • begin • if(B_hold) • begin • done=1'b0; • GCD=8'h00; • end • else • begin • done=1'b1; • GCD=A_hold; • end • end

  8. Modesim仿真结果 采用以下三组数据对电路的行为功能模拟

  9. A=21，Ｂ＝4９，GCD=7

  10. A=25,B=25 GCD=5

  11. A=250,B=190 GCD=10

  12. 结果讨论 • 计算所用的时间不一样，且差距很大，是GCD的最大的问题。

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