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Topics of Lecture

Topics of Lecture. Configuration Test Bench Encapsulation Structural Decomposition. TestBench. Testbench Example. Configuration Clock Test Bench Behavioral to Structural After J. Pick, VHDL Techniques, Experiments, and Caveats, McGraw-Hill, 1996. Counter Test Bench Entity.

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Topics of Lecture

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  1. Topics of Lecture • Configuration • Test Bench • Encapsulation • Structural Decomposition

  2. TestBench

  3. Testbench Example • Configuration • Clock • Test Bench • Behavioral to Structural • After J. Pick, VHDL Techniques, Experiments, and Caveats,McGraw-Hill, 1996.

  4. Counter Test Bench Entity entity Counter_Wrapper_TB is end Counter_Wrapper_TB ; No port clause since encapsulating counter to test it.

  5. First Counter Architecture architecture Count_1 of Counter_Wrapper_TB is signal Clock :bit := ‘0’; begin

  6. Local Clock Clock_P_1 :process begin Clock <= not Clock after 50 ns; wait on Clock ; end process Clock_P_1 ;

  7. Counter Process Inc_Cntr:process variable Count_Now :integer := 0; begin --wait for trailing edge wait until Clock = ‘0’ ;

  8. Increment Counter --increment mod 8 if Count_Now = 7 then Count_now := 0 ; else Count_now := Count_Now + 1 ; end if ; end process Inc_Cntr ; end Count_1 ;

  9. 2nd Counter Architecture architecture Count_2 of Counter_Wrapper_TB is signal Clock :bit := ‘0’; begin -- no change

  10. Local Clock with Static Sensitivity List Clock_P_2 :process ( Clock) begin Clock <= not Clock after 50 ns; -- removed ... wait on Clock ; end process Clock_P_2 ;

  11. Counter Process Inc_Cntr:process variable Count_Now :integer := 0; begin --wait for trailing edge wait until Clock = ‘0’ ; -- no change

  12. Increment Counter --increment mod 8 if Count_Now = 7 then Count_now := 0 ; else Count_now := Count_Now + 1 ; end if ; -- no change end process Inc_Cntr ; end Count_2 ; -- no change

  13. 3rd Counter • Same As Others Except for Clock Generator • Concurrent Clock Instead of Process • Wrapper Slides Not Repeated Here

  14. Concurrent Local Clock Clock_P_3 : -- removed process ( Clock) -- removed begin Clock <= not Clock after 50 ns; -- removed ... wait on Clock ; -- removed end process Clock_P_2;

  15. Specific Configuration of Counter configuration Conf_KJH_1 of Counter_Wrapper_TB is --no ambiguity here --only one entity per library for Count_1 --ambiguity so need to --specify architecture

  16. End Configuration end for ; end Conf_KJH_1 ; --architecture is now bound --to entity

  17. Encapsulation Conf_KJH_1 Counter_Wrapper_TB Count_1

  18. 2nd Specific Configuration of Counter configuration Conf_KJH_2 of Counter_Wrapper_TB is --no ambiguity here --only one entity per library for Count_2 --ambiguity so need to --specify architecture

  19. End Configuration end for ; end Conf_KJH_2 ; --different architecture is --now bound to same entity --mutually exclusive bindings

  20. Encapsulation Conf_KJH_2 Counter_Wrapper_TB Count_2

  21. Encapsulation Counter_Wrapper_TB Count_? Conf_KJH_? Count_1 Count_2 Architectures Count_3

  22. Structural Decomposition of Counter_Wrapper_TB Counter_Wrapper_TB Clock Counter Verify Counter_Wrapper_TB Count_3

  23. SD Counter Clock Component architecture Count_SD of Counter_Wrapper_TB is component Clock generic (PW :time) ; port ( Clock :out bit); end component Clock ;

  24. SD Counter Component component Counter_Mod_8 port ( Clock :in bit; DataOut :out bit_vector (2 downto 0 )); end component Counter_Mod_8 ;

  25. SD Verify Component component Verify port ( DataIn :in bit_vector (2 downto 0 )); end component Verify ;

  26. SD Signals signalClock_Tic :bit := ‘0’ ; signalCount_Data :bit_vector (2 downto 0 ) :=(others => ‘0’ ); --initializes all values to ‘0’

  27. Clock Instantiation begin Synch : Clock generic map ( PW => 50 ns ) --no ; required cause port next port map ( Clock_Tic ) ;

  28. Counter Instantiation Counter_Instance : Counter_Mod_8 port map ( Clock_Tic,Count_Data ) ;

  29. Verify Instantiation Verify_Instance : Verify port map ( DataIn => Count_Data ) ; end Count_SD ;

  30. Block Diagram of SD Verify DataIn (2) DataIn (1) DataIn (0) Count_SD Clock out Counter_Mod_8 Clock in DataOut (2) DataOut (1) DataOut (0)

  31. Approach • Turn Counter_Mod_8 into an entity and put in a library after it has been verified • Count_SDis a good start to a testbench where the counter drives a signal generator which creates the sequential signals to excite the device under test • Verifyis a component which needs to be expanded with assert/report statements to verify performance

  32. End of Lecture • Configuration • Test Bench • Structural Decomposition

  33. Sources Prof. K. J. Hintz Department of Electrical and Computer Engineering George Mason University

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