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Dataflow Modeling of Signal Processing and Communication Systems. Prof. Brian L. Evans Guest Lecture for EE 382V Embedded System Design and Modeling. Outline. 2. Introduction Signal processing system design needs Synchronous dataflow Signal processing building blocks Filters
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Wireless Networking and Communications Group Dataflow Modeling ofSignal Processing and Communication Systems Prof. Brian L. Evans Guest Lecture forEE 382V Embedded System Design and Modeling
Outline 2 • Introduction • Signal processing system design needs • Synchronous dataflow • Signal processing building blocks • Filters • Rate changers • Signal processing examples • Communication system examples • Conclusion
Needs for System-Level Design Signal processing algorithms Multirate processing: e.g. interpolation Local feedback: e.g. IIR filters Iteration: e.g. decoding Graphical representations Block diagram syntax natural but static Dataflow semantics for signal processing Signal representations Bit, byte, integer, fixed-point, floating-point Complex-valued versions of above Vectors/matrices of scalar data types Bit error rate vs. Signal-to-noise ratio (Eb/No) Often iterative Do not needrecursion
Needs for Embedded Realization Block-based and point-by-point processing Retarget simulation for embedded platforms Processors (e.g. DSPs) and hardware (e.g. FPGAs) Cosimulation on desktop and embedded platforms Static scheduling Prediction of resources (e.g. memory) at compile time DSPs have limited on-chip memory (32-512 kB) FPGAs have limited on-board memory & logic blocks Floating-point to fixed-point conversion 4
Dataflow Models Match data-intensive processing Signal processing Communication systems Definitions [Lee] A token is a data value or data structure A signal is a sequence of tokens A node maps input tokens onto output tokens Set of firing rules specify when a node can fire A firing of a node consumes input tokens and produces output tokens A sequence of firings is a dataflow process 5
Synchronous Dataflow [Lee 1987] Untimed Arcs: one-way first-in first-out (FIFO) queues Nodes: functional blocks Source nodes always enabled Others enabled when enoughsamples are on all inputs Node execution Consumes same fixed number of samples on each input arc Produces same fixed number of tokens on each output arc Consumed data is dequeued from arc Flow of data through graph does not depend on data values 3 2 A B 6
Synchronous Dataflow (SDF) Delay of (n) samples n samples initially in FIFO queue Systems are determinate Execution in sequence or parallelhas same outcome (predictable) Systems can be statically analyzed Check for “sampling rate” consistency Determine/optimize FIFO queue sizes atcompile time Models systems with rational rate changes Periodic schedule fires A twice & B thrice, e.g. AABBB or ABABB 3 2 A B 3 (6) 2 Nodes are not multirate but graph is! 7
Outline Introduction Signal processing system design needs Synchronous dataflow Signal processing building blocks Filters Rate changers Signal processing examples Communication system examples Conclusion 9
Homogeneous Operations Pointwise arithmetic operations (addition, etc.) Delay by m samples property of SDF arc Finite impulseresponse filter 1 1 1 1 op 1 1 1 1 1 … … 1 S FIR
Homogeneous Operations Infiniteimpulseresponsefilter b0 a1 b1 aM a2 b2 bN x[k] y[k] UnitDelay UnitDelay x[k-1] y[k-1] UnitDelay UnitDelay x[k-2] y[k-2] Feed-forward Feedback UnitDelay UnitDelay IIR x[k-N] y[k-M]
Increasing Sampling Rate Upsampling by Ldenoted asL Outputs input sample followed by L-1 zeros Increases sampling rate by factor of L Finite impulse response (FIR) filter g[m] Fills in zero values generated by upsampler Multiplies by zero most of time(L-1 out of every L times) Sometimes combined intorate changing FIR block 1 1 4 1 g[m] 4 Input to Upsampler by 4 n 0 1 2 Output of Upsampler by 4 m 0 1 2 3 4 5 6 7 8 1 4 FIR Output of FIR Filter m 0 1 2 3 4 5 6 7 8 12
Polyphase Filter Bank Form Filter bank (right) avoids multiplication by zero Split filter g[m] into L shorter polyphase filters operating at lower rate (no loss in output precision) Saves factor of L in multiplications and prev. inputs stored and increases parallelism by factor of L Oversampling filter a.k.a. Pulse shaper a.k.a. Linear interpolator g0[n] s(Ln) 1 L g1[n] L 1 s(Ln+1) g[m] L Multiplies by zero (L-1)/L of the time gL-1[n] s(Ln+(L-1)) 13
Decreasing Sampling Rate Finite impulse response (FIR) filter g[m] Typically a lowpass filter Enforces sampling theorem Downsampling by Ldenoted asL Inputs L samples Outputs first sample and discards L-1 samples Decreases sampling rate by factor of L Sometimes combined intorate changing FIR block Input to Downsampler m 0 1 2 3 4 5 6 7 8 Output of Downsampler n 0 1 2 1 1 4 1 g[m] 4 4 1 FIR
Polyphase Filter Bank Form Filter bank (right) only computes values output Split filter h[m] into M shorter polyphase filters operating at lower rate (no loss in output precision) Saves factor of M in multiplications and increases parallelism by factor of L 1 s(Mn) Undersampling filter a.k.a. Matched filter + sampling a.k.a.Linear decimator h0[n] s(Mn+1) h1[n] M 1 M h[m] M hM-1[n] Outputs discarded (M-1)/M of the time s(Mn+(M-1)) 15
Outline Introduction Signal processing system design needs Synchronous dataflow Signal processing building blocks Filters Rate changers Signal processing examples Communication system examples Conclusion 16
Spectral Shaping for Converter Upsampling by 4 Output input sample then 3 zeros Increases sampling rate fourfold FIR filter performs interpolation [Pohlmann] 176.4 kHz FIR Filterfstop< 22.05 kHz 16 bits176.4 kHz 4 Digital 4x Oversampling Filter Spectral shapingfor an audio data converter 17
Noise-Shaped Feedback Coding Homogeneous. Computable? Original Image Threshold at Mid-Gray Noise-Shaped difference quantizer u(m) b(m) + x(m) _ _ e(m) + shapeerror (noise) compute error (noise) Sigma-delta modulator using noise-shaped feedback coding (spectral shaping)
Outline Introduction Signal processing system design needs Synchronous dataflow Signal processing building blocks Filters Rate changers Signal processing examples Communication system examples Conclusion 19
Communication Systems Message signal m[k] is information to be sent Information may be voice, music, images, video, data Low frequency (baseband) signal centered at DC Transmitter signal processing includes lowpass filtering to enforce transmission band Transmitter carrier circuits upconvert signal SignalProcessing CarrierCircuits Transmission Medium Carrier Circuits SignalProcessing s(t) r(t) TRANSMITTER CHANNEL RECEIVER 20
Communication Systems Propagating signals experienceattenuation & spreading w/ distance Receiver carrier circuits downconvert to an intermediate frequency and possibly baseband Receiver signal processing extracts/enhances baseband signal SignalProcessing CarrierCircuits Transmission Medium Carrier Circuits SignalProcessing s(t) r(t) TRANSMITTER CHANNEL RECEIVER Model the environment 21
Quadrature Amplitude Modulation SignalProcessing CarrierCircuits Transmission Medium Carrier Circuits SignalProcessing s(t) r(t) TRANSMITTER CHANNEL RECEIVER i[n] L gT[m] Index Bits Pulse shaper(FIR filter) cos(0m) Serial/parallelconverter Map to 2-D constellation + J 1 Digital QAM Transmission L gT[m] q[n] L samples per symbol (upsampling) sin(0m) 22
Quad. Amplitude Demodulation SignalProcessing CarrierCircuits Transmission Medium Carrier Circuits SignalProcessing s(t) r(t) TRANSMITTER CHANNEL RECEIVER Digital QAM Reception iest[n] hopt[m] L Matched filter(FIR filter) cos(0m) Parallel/serialconverter DecisionDevice heq[m] 1 J Symbol Bits Channel equalizer (FIR filter) hopt[m] L qest[n] L samples per symbol (downsampling) sin(0m) 23
Modeling of Points In-Between Baseband channel model Combines transmitter carrier circuits, channel and receiver carrier circuits One model uses cascadeof gain, FIR filter, andadditive noise(homogeneous SDF) SignalProcessing CarrierCircuits Transmission Medium Carrier Circuits SignalProcessing s(t) r(t) TRANSMITTER CHANNEL RECEIVER FIR + noise
Limitations of SDF Strengths of SDF are also its limitations Untimed Predictable flow of data through graph Modeling of receiver front end Automatic gain control (AGC) Symbol clock recovery (digital IIR) Receive filter (analog IIR) CarrierDetect AGC Analog front end for QAM reception Receive Filter A/D Symbol Clock Recovery 25
Conclusion Synchronous dataflow model does not support Composability with itself Data-dependent graphs Recursion Advantages Models multirate systems Ability to generate static schedules at compile time (resources required by graph known in advance) Static sequential schedules can be optimized for minimum program memory or buffer memory SDF modeling allows efficient simulation and synthesis SDF well-matched to signal processing and communications Limited expressiveness enables SDF to be statically scheduled Synchronous dataflow is untimed and determinate 26
27 Thank You, Questions ?