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Simulazione atomistica di FET a nanowire in silicio

Simulazione atomistica di FET a nanowire in silicio. A. Pecchia , Aldo Di Carlo. Dipartimento di Ingegneria Elettronica, Università di Roma “Tor Vergata”. Dispositivi FET a Si nanowire. D. D. D. Ma. et al. , Science , vol. 299, pp. 1874-1877, 2003.

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Simulazione atomistica di FET a nanowire in silicio

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  1. Simulazione atomistica di FET a nanowire in silicio A. Pecchia,Aldo Di Carlo Dipartimento di Ingegneria Elettronica, Università di Roma “Tor Vergata”

  2. Dispositivi FET a Si nanowire D. D. D. Ma. et al., Science, vol. 299, pp. 1874-1877, 2003 SiO2 shells has been removed and silicon is terminated with H Coaxially gated Si nanowire FET L. J. Lauhon, et al., Nature, vol. 420, pp. 57-61, 2002. Silicon Nanowires (SiNW) represents good candidates for the ultimate scaling of MOSFET

  3. Problematiche nel trasporto • Confinamento quantistico ? • Interfaccia Si/SiO2 , SiH ? • Proprietà di screening ? • Trasporto balistico ? • Electron-phonon scattering ? • … ? Per avere risposte a queste domande …

  4. 6 nm 1.2 nm (2.4 nm) 3.6 nm oxide P doped region P doped region Intrinsic region oxide Source Drain 7.7 nm Simulazioni: Gate all-around SiNW FET …(e non solo!) il poster vi introdurrà nel mondo delle simulazioni atomistiche.

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