Delay/Phase Regeneration Circuits

1. Delay/Phase Regeneration Circuits Crescenzo D’Alessandro, Andrey Mokhov, Alex Bystrov, Alex Yakovlev Microelectronics Systems Design Group School of EECE Newcastle University, UK

2. Outline • Introduction • Background on Phase-encoding • Dual-rail/multiple-rail phase encoding • Motivation for the present work • Taxonomy • Latch-based designs • MUTEX-based designs • Design types • Conclusions

3. t_1 before t_0 t_0 before t_1 ref t_1 t_0 sp0 sp0 sp1 sp0 sp1 data 0 0 1 0 Phase EncodingDual-Rail • Main idea: encode data on the phase relationship between two identical out-of-phase signals • Resistant to transient faults • Similarity with dual-rail dual-spacer protocol

4. Multiple Rail • No group of wires has the same delay • All wires toggle when an item of data is sent

5. Phase Corruption • Phase corruption is due to jitter (introduced by the gates), physical wire fabric and transistor mismatches • Mismatch in process variations cause a systematic delay offset to appear between the two lines, which could cause errors in decoding • Additionally, cross-talk causes symbol-dependent phase corruption • As the wires are always “allies” in terms of cross-talk, the longer the wire, the more corrupted the phase relationship between the wires • What is then the optimal length of wire which “guarantees” that the phase relationship is maintained?

6. Phase Corruption • Example of phase corruption • No change in sequence • Change in absolute value of phase

7. Taxonomy • Different design styles can be identified • We focus in this presentation on digital implementations • Latch-based designs • A latch is used on each wire • Gate-level implementation • Transistor-level implementation • MUTEX-based designs • A single MUTEX is used to arbitrate between the two edges • “Early-propagating” • “Merging”

8. Parameters • Maximum input time separation affected δmax • Events whose time separation is > δmax retain their original separation • Circuit latency λ • Time between the first event occurring and the corresponding output being generated • Response time ζ • Time between the two events below which the time separation cannot be regenerated • Capture range κ= δmax – ζ • Using the convention sometimes used in PLLs to give a value for the range • Linearity

9. Graphs δmax ζ Linearity: how flat this part is λ κ

10. Passive Solution • “Textbook” solution • Different response for rising/falling – can be matched using balanced drivers • Not very linear • Capacitor size a problem – also introduces latency

11. Latch-basedGate level/1

12. Latch-basedGate level/1 • Latches are transparent at startup • They are closed after one edge arrives at the output • They are then reopened after the pulse is finished • 6 FO4 capture range, stops working around 5 FO4 input delta • Difference in rising and falling behaviour

13. Latch-basedGate level/2 • Similar to previous design • Two pulse generators – faster • Only blocks one output and not both • Only one output used – less difference between rising and falling edges

14. Latch-basedTransistor level

15. Latch-basedTransistor level • Better latency and response • Capture range can be increased increasing tau • Good linearity

16. MUTEX-based

17. MUTEX-based • Higher latency (complex gates) • Good response and capture range • Poor linearity • Early-propagating

18. MUTEX-based • “Infinite” capture range – lower-bounded • Flat response • Very high latency – dependent on input time separation • NOR-MUTEX is slow

19. STG for Repeater • STG for a repeater • Use timing assumptions: • i1- -> p1 -> g11-, g12- • g11- -> i1+ • … and mirror ones • This STG can be synthesised using PETRIFY • Synthesised version in next slide…

20. MUTEX-basedw/PETRIFY • Very good linearity and capture range • High latency independent on input until 0.5 FO4 • Generated using PETRIFY (STG in previous slide)

21. TSE • Transition Sequence Encoder • This circuit generates a number of requests based on an input matrix • The acknowledgments can be either “proper” or a delayed version of the output signals • Can be used as a phase-encoder

22. MUTEX-TSE • This solution is similar to the MUTEX-based one, only using the TSE as a sender • λ < 2 FO4 • Increasing output time separation dependent on the input (output δ > 8FO4)

23. TSE – Transistor-level • Like above, only rising and falling edge • Transistor-level implementation of the TSE • Results similar to the previous case • Note the similarity with the transistor-level latch-based design

24. Multiple-rail • Multiple-rail phase-encoding requires similar designs to regenerate the phase relationship • The design on the right is a simple expansion of the previous latch-based design • Very slow response • Only useful for large δ • Acceptable latency

25. Multiple-rail “merge” • Better design: use a TSE • Shown: 3-wires regeneration – left, rising edge only, right; rising and falling edges • Better response, but λ depends on the input time separation (needs to wait for all inputs to be present)

26. Performance comparison • Dual-rail implementations • Area in transistor count • κ and λ in FO4 • Area and energy for “Latch-based transistor level” design is for no keeper/keeper • “Charge compensation”: area calculated estimating the size of the capacitors • Avg. for rise/fall

27. Conclusions • Some phase-regeneration circuits have been presented • More work to do: • Metastability behaviour, in particular for keeper structures • Behaviour in case of faults • Characterisation with different input signal slopes

28. Contact details Crescenzo S. D’Alessandro Microelectronics Systems Design Group School of Electrical, Electronics and Computer Engineering Merz Court Newcastle University, UK Crescenzo.D’Alessandro@ncl.ac.uk http://async.org.uk