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Technology Scale Down: Who's Who, Roadmap, MOS Device, Inverter, Conclusion

This article provides a detailed overview of the technology scale down process, including information on industry leaders, roadmap timelines, MOS device characteristics, inverter performance, and the overall benefits of scaling down technology. The text is written by E. Sicard and emphasizes the continuous growth in frequency, reduction in power supply, improved interconnect density, and upcoming advancements in 0.12µm technology.

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Technology Scale Down: Who's Who, Roadmap, MOS Device, Inverter, Conclusion

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  1. 1. Illustration of the Technology Scale down Etienne Sicard etienne.sicard@insa-tlse.fr http://intrage.insa-tlse.fr/~etienne

  2. Summary 1. Who’s who 2. Road map 3. The MOS device 4. The inverter 5. Conclusion E. Sicard - Technology scale down

  3. 1. Who’s who in France Philips Philips Ibm ST rennes Atmel Atmel ST Grenoble ST Tours Texas, VLSI Cadence ST, Atmel Motorola E. Sicard - Technology scale down

  4. 2. Roadmap Bits 4G 10 GIGA DRAM 1G 256M 1 GIGA 64M 100 MEG 16M 4M 10 MEG 1M 1 MEG 256K 100K Year 83 86 89 92 95 98 01 04 Année E. Sicard - Technology scale down

  5. 2. Roadmap Technology (µm) 2.0 Production 80286 80386 1.0 486 pentium pentium II 0.3 0.2 Pentium IV Research 0.1 0.05 0.03 83 86 89 92 95 98 01 04 Year E. Sicard - Technology scale down

  6. 2. Roadmap Leti 1 MOS 0.02µm Dec. 2000 IBM 106 MOS 0.015µm Nov. 2001 E. Sicard - Technology scale down

  7. 8 layers 7 layers 2. Roadmap 0.5 µm 0.18 µm 0.12µm l Devices 1995 2000 2002 3 layers Interconnects Frequency 1500 MHz 120MHz 500MHz E. Sicard - Technology scale down

  8. 2. Roadmap E. Sicard - Technology scale down

  9. I/O trend Core trend 2. Roadmap Supply (V) Chip I/Os 5.0 3.3 Chip Core 2.5 1.5 Technology (µm) 0.5 0.35 0.18 0.10 0.07 E. Sicard - Technology scale down

  10. 2. Roadmap Radiation Typical wire load (fF) 100 75 50 Charge 25 Charges (C.V) Technology (µm) 0.5 0.35 0.18 0.10 0.07 “Soft error” due to radiation becomes probable E. Sicard - Technology scale down

  11. 3. The MOS device 3 1 2 I V 3 demo 2 1 Little quiz V E. Sicard - Technology scale down

  12. 3. The MOS device 0 1 0 1 demo Ron close from 1000 E. Sicard - Technology scale down

  13. 1 1 1 0 Good 0 Bad 1 0 0 1 0 Good 1 Bad 0 3. The MOS device Technology scale down keeps those drawbacks E. Sicard - Technology scale down

  14. Static Current (A) 1 0.1 0.01 0.001 Low leakage MOS 3. The MOS device R off 100 M 1 MT block 10 M 1 M 100K Technology (µm) 0.5 0.35 0.18 0.10 0.07 E. Sicard - Technology scale down

  15. 3. The MOS device Low power High Speed High Voltage 3.3V E. Sicard - Technology scale down

  16. 4. The inverter In Out Time • In 0.25µm typical delay 50ps • Depends on conditions (10,90%) • Depends on charge (capacitance) demo E. Sicard - Technology scale down

  17. 4. The inverter Idd (mA) In, Out (V) Time • Current peaks 0.2mA E. Sicard - Technology scale down

  18. 4. The inverter Delay (ns) Interconnection (µm) E. Sicard - Technology scale down

  19. 4. The inverter Ring oscillator 0.7µm 0.25µm Frequencies x 5 although VDD divided by 2 E. Sicard - Technology scale down

  20. Conclusion • Illustration of technology scale down • Continuous gain in frequency • Power supply reduction • The MOS keeps the same, but many versions • Increased interconnects improve density • In 2002, ST will produce the 0.12µm technology E. Sicard - Technology scale down

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