OPERATING SYSTEM CONCEPTS

OPERATING SYSTEM CONCEPTS 操作系统概念 13. I/O Systems 张柏礼 bailey_zhang@sohu.com 东南大学计算机学院

13. I/O Systems • Objectives • Explore the structure of an operating system’s I/O subsystem • Discuss the principles of I/O hardware and its complexity • Provide details of the performance aspects of I/O hardware and software

13. I/O Systems • 13.1 Overview • 13.2 I/O Hardware • 13.3 Application I/O Interface • 13.4 Kernel I/O Subsystem • 13.5 Transforming I/O Requests to Hardware Operations • 13.6 STREAMS • 13.7 Performance

13.1 Overview • I/O System of OS • The main job of a computer is I/O • The role of the OS in I/O is manage and control • I/O devices • I/O devices vary so widely in their function and speed • Hard disk vs. keyboard • Varied methods are needed to manage and control them • These methods form the I/O subsystem of the kernel • I/O operation

13. I/O Systems • 13.1Overview • 13.2 I/O Hardware • 13.3 Application I/O Interface • 13.4 Kernel I/O Subsystem • 13.5 Transforming I/O Requests to Hardware Operations • 13.6 STREAMS • 13.7 Performance

13.2 I/O Hardware • I/O Hardware • Devices • Connections • for devices communicating with a computer system (main memory)

13.2 I/O Hardware • General categories of I/O devices • Storage devices • Disks, tapes • Transmission devices • Network cards, modems • Human-interface devices • Screen, keyboard, mouse • Specialized devices • The steering of fighter, a space shuttle

13.2 I/O Hardware • Connections (Attachments) • Port • A connection point • serial port, a parallel port • Bus (daisy chain or shared direct access) • A set of wires and a rigidly defined protocol • PCI, ISA, SCSI • Device Controller • Is a collection of electronics that can operate a port, a bus or a device • Serial port controller • SCSI bus controller • IDE controller

13.2 I/O Hardware A typical PC bus structure

13.2 I/O Hardware • I/O transfer (Data transfer) • Registers • Typically I/O controller has 4 types of registers • Status registers • Control registers • Data-in registers • Data-out registers • These device registers have addresses, that can be accessed by processor

13.2 I/O Hardware • Reading and Writing of registers • Special I/O instructions (Direct I/O) • Transfer a byte or a word to an I/O port address • Trigger bus lines to select the proper device • Move bits into or out of a device register • Memory-mapped I/O • Device registers are mapped into the memory address • Use the standard data-transfer instructions to read and writer the registers • Direct I/O + memory mapped I/O

13.2 I/O Hardware Device I/O Port Locations on PCs (partial)

13.2 I/O Hardware • Interaction protocol (Handshaking protocol between the host and a control) • Three interaction models between I/O controllers and CPUs to accomplish an complete I/O transfer • Polling （问答式） • Interrupt • DMA

13.2 I/O Hardware • Polling • PIO (programmed I/O， Polling) • An example • Two bits • The busy bit in the status register • indicates if the controller is busy or not. • The command-ready bit in the control/command register • indicates if the a command is available or not for the controller to execute.

13.2 I/O Hardware • Handshaking mechanism works as follows (the host writes output through a port): • The hostrepeatedly reads the busy bit until that it becomes clear (busy waiting or polling) • The host sets the writing bit(正在写) in the control/command register (availably for reading command) and writes a byte into the data-out register • The host sets the command-ready bit in the control/command register

13.2 I/O Hardware • When the controller notices that the command-ready bit is set, it sets the busy bit (in status register) • The controller reads the command register and gets the write command. It reads the data-out register to get the byte, and does the I/O to the device. • The controller clears the command-ready bit, clears the error bit in the status register to indicate that the device I/O succeeded, and clears the busy bit to indicate that it is finished.

13.2 I/O Hardware • Interrupts • Disadvantage of polling • Polling becomes inefficient when it rarely finds a device to be ready for service • It may be more efficient for controller to notify the CPU when the device becomes ready for service ————interrupt • Interrupt mechanism • After executing every instruction, the CPU senses the interrupt-request line to find whether a control has asserted a signal on the line • The CPU performs a state save and jumps to the interrupt-handler routine at a fixed address in memory

13.2 I/O Hardware • Interrupt handler • determines the cause of interrupt • Performs the necessary processing • Performs a state restore • Executes a return from interrupt instruction to return the CPU to the execution state prior to the interrupt • receives interrupts • The basic interrupt mechanism enables the CPU to respond to an asynchronous event

13.2 I/O Hardware Interrupt-Driven I/O Cycle

13.2 I/O Hardware • More complex interrupt features is needed in modern OS • Be able to defer interrupt handling during critical processing • Need an efficient way to dispatch to the proper interrupt handler for device without polling all the devices to see which one raised the interrupt • Be able to distinguish between high-priority and low-priority interrupts and respond with the appropriate degree of urgency ——these are provided by CPU and interrupt-controller hardware

13.2 I/O Hardware • Two interrupt request lines • Nonmaskable interrupt line • For events such as unrecoverable memory errors • Maskable interrupt line • For device controllers • It can be turned off by the CPU before the execution of critical instruction • Interrupt vector • Contains the memory addresses of specialized interrupt handlers • Reduces the need for a interrupt handler to search all possible sources of interrupts

13.2 I/O Hardware • Interrupt chaining：computers have more devices (interrupt handler) than address elements in the vector • Each type of devices has an elements in vector • Each element points to the head of a list of interrupt handlers • When an interrupt is raised, the handlers one the list are called one by one, until one is found that can serve the request • The chain structure is compromise between the overhead of a huge interrupt vector and inefficiency search for a interrupt handler

13.2 I/O Hardware Intel Pentium Processor Event-Vector Table

13.2 I/O Hardware • Interrupt priority level • Enable the CPU to defer the handling of low-priority interrupts without masking off all interrupt • Enable the high-priority to preempt the execution of a low-priority interrupt • A threaded kernel architecture is well suited to implement multiple interrupt priorities

13.2 I/O Hardware • Interrupt mechanism also used for • exceptions • Dividing by zero, accessing a protected or nonexistent address, executing a privilege instruction for users • Induce the CPU to execute an urgent, self-contained routine • Page fault • saves a small amount of processor state and then call a privileged routine in the kernel

13.2 I/O Hardware • system calls • Software interrupt, trap • When a process executes the trap instruction • Interrupt hardware saves the state of the user code, switcher to supervisor mode and then dispatches to the kernel routine • The trap is given a relatively low interrupt priority compared with device interrupts——executing a system call on behalf of an application • Manage the flow of control within the kernel Sum: Interrupts are used throughout modern operating systems to handle asynchronous events and to trap to supervisor-mode routines in the kernel

13.2 I/O Hardware • Direct Memory Access (DMA) • PIO (programmed I/O， Polling) • Use CPU to watch status bit and feed data into a controller register one byte at a time • It seems wasteful to do large data transfer for an expensive general-purpose processor • DMA controller • Offloading some PIO to a special-purpose processor called a DMA controller • To initiate a DMA, • the CPU writes a command block into memory • A pointer to the source, a pointer to the destination, and the number of bytes to be transferred • The CPU writes the address of this command block to the DMA controller, and goes on with other work

13.2 I/O Hardware Six Step Process to Perform DMA Transfer

13.2 I/O Hardware • Bypasses CPU to transfer data directly between I/O device and memory • Cycle stealing (周期挪用) • When DMA control seizes the memory bus, the CPU is prevented from accessing main memory • It slow down the CPU computation, but improves the total system performance

13.3 Application I/O Interface A Kernel I/O Structure

13.3 Application I/O Interface • Device drivers • Custom-tailored to each device, hide the differences among device controllers from the I/O subsystem • Present a uniform device-access interface to the kernel I/O subsystem

13.3 Application I/O Interface • Kernel I/O • Provides numerous services • I/O scheduling, buffering, caching, spooling • System calls • Encapsulate the behavior of devices in a few generic class to hide hardware differences from application • provide a standard interface between the application and the OS • Kernel I/O structure • Devices vary in many dimensions • Character-streamorblock • Sequentialorrandom-access • Sharableordedicated • Speed of operation • read-write, read only, orwrite only

13.3 Application I/O Interface Characteristics of I/O Devices

13.3 Application I/O Interface • For the purpose of application access • the devices are grouped into a few types/ classes • I/O system calls encapsulate device behaviors in generic classes • Device-driver layer hides differences among I/O controllers from kernel

13.3 Application I/O Interface • Each type is accessed through a standardized set of functions——an interface • Convention system call to access • Block I/O • Character-stream I/O • Memory-mapped file access • Network sockets • Special system call to access • Time-of-day clock • Timer • Graphical display

13.3 Application I/O Interface* • Block and Character Devices • Block devices include disk drives and other block-oriented devices: • Commands include read, write, seek • Raw I/O or file-system access • Memory-mapped file access possible • Character devices include keyboards, mice, serial ports • Commands include get(), put() • Libraries layered on top allow line editing

13.3 Application I/O Interface • Network Devices • Varying enough from block and character to have own interface • Unix and Windows NT/9x/2000 include socket interface • Separates network protocol from network operation • Includes select() functionality • Approaches vary widely (pipes, FIFOs, streams, queues, mailboxes)

13.3 Application I/O Interface • Clocks and Timers • Provide current time, elapsed time, timer • Programmable interval timerused for timings, periodic interrupts • ioctl() (on UNIX) covers odd aspects of I/O such as clocks and timers

13.3 Application I/O Interface • Blocking and Nonblocking I/O • Blocking - process suspended until I/O completed • Easy to use and understand • Insufficient for some needs • Nonblocking (1) I/O call returns as much as available • User interface, data copy (buffered I/O) • Implemented via multi-threading • Returns quickly with count of bytes read or written (2) Asynchronous - process runs while I/O executes • Difficult to use • I/O subsystem signals process when I/O completed

13.3 Application I/O Interface Two I/O Methods

13.4 Kernel I/O Subsystem* • Kernel provide several services to I/O • I/O scheduling • Buffering • Caching • Spooling and device reservation • Error handling • Kernel data structures

13.4 Kernel I/O Subsystem • I/O Scheduling • I/O request queue for a device • Some OS’s try fairness(disk I/O) • Buffering • store data in memory while transferring between devices • To cope with device speed mismatch • To cope with device transfer size mismatch • To maintain “copy semantics”

13.4 Kernel I/O Subsystem Device-status Table

13.4 Kernel I/O Subsystem Sun Enterprise 6000 Device-Transfer Rates

13.4 Kernel I/O Subsystem • Caching • fast memory that holding copies of data • Always just a copy • Key to performance • Note: A buffer may hold the only existing copy of a data item, whereas a cache just holds a copy on a faster storage of an item that that resides elsewhere. • Spooling • hold output for a device • If a device can serve only one request at a time • i.e., Printing

13.4 Kernel I/O Subsystem • Device reservation • provides exclusive access to a device • System calls for allocation and de-allocation • Watch out for deadlock • Error handling • OS can recover from disk read, device unavailable, transient write failures • Most return an error number or code when I/O request fails • System error logs hold problem reports

13.4 Kernel I/O Subsystem • I/O Protection • User process may accidentally or purposefully attempt to disrupt normal operation via illegal I/O instructions • All I/O instructions defined to be privileged • I/O must be performed via system calls • Memory-mapped and I/O port memory locations must be protected too

13.4 Kernel I/O Subsystem Use of a System Call to Perform I/O

OPERATING SYSTEM CONCEPTS