National Sun Yat-sen University Embedded System Laboratory

1. National Sun Yat-sen University Embedded System Laboratory Automated Conformance Evaluation of SystemC Designs using Timed Automata Presenter: Ming-Shiun Yang PaulaHerber,MarcelPockr and tandSabineGlesner BerlinInstituteofTechnology(TUBerlin),Germany Test Symposium(ETS), 2010 15th IEEE European 2012/10/22

2. Abstract SystemC is widely used for modeling and simulation in hardware/software co-design. However, the co-verification techniques used for SystemC designs are mostly ad-hoc and non-systematic. A particularly severe drawback is that simulation results have to be evaluated manually. In previous work, we proposed to overcome this problem by conformance testing. We presented an algorithm that uses an abstract SystemC design to compute expected output traces, which are then compared with those of a refined design to evaluate its correctness. The main disadvantage of the algorithm is that it is very expensive because it computes the output traces offline and has to cope with nondeterministic systems. Furthermore, the designer has to compare the results manually with the outputs of a design under test. In this paper, we present an approach for efficient and fully-automatic conformance evaluation of SystemC designs. To achieve this, we first present optimizations of our previously proposed algorithm for the generation of conformance tests that drastically reduce computation time and memory consumption. The main idea is to exploit the specifics of the SystemC semantics to reduce the number of semantic stats that have to be

3. Abstract (cont.) kept in memory during state-space exploration. Second, we present an approach to generate SystemC test benches from a set of expected output traces. These test benches allow fully-automatic test execution and conformance evaluation. Together with our previously presented model checking framework for abstract SystemC designs, we yield a fully-automatic HW/SW co-verification framework for SystemC that supports the whole design process. We demonstrate the performance and error detecting capability of out approach with experimental results.

4. What’s the problem • The conformance test of previous work had to be done manually. • This paper change this to automatically. • The previous work can only handle small designs. • Because the same state-space explosion problem increase the memory consumption. • This paper present an optimized conformance test algorithm to reduce the memory consumption so that it can handle large designs.

5. Related Work [5] Model Checking and Testing [4] Model Checking Reduce memory consumption Automate Conformance Testing This paper

6. Proposed-Model checking and Conformance testing framework Model Checking Uppaal Model Conformance Testing Consist of an input generator and a generic tester Map the informally defined semantics of SystemC to the formally well-defined semantics of Uppaal timed automata Verify that the Uppaal model fulfills the properties defined in the requirements specification

7. Conformance Test Generation Uppaal Model 2 1 3 4

8. Test Benches for Conformance Evaluation Refined Model Look-up-table : Possible output traces and the corresponding time information Output port • If the output port provide only blocking read access, a monitor process will be infinitely blocked. • They use multiple monitor processes.

9. Timing Monitor in SystemC Lower Bound Upper Bound Fail OK Fail • Lower/Upper Bound are get from LUT.

10. Experiment result – Effort of Conformance Test Generation • Run on Intel Pentium 3.4GHz CPU and 4GB main memory. • ABS/ASR system is refined by using a high-speed CAN bus, and detail timing information. System complexity Can not handle in reasonable time Run out of memory

11. Experiment result – Error Detecting Capability Injected defect • “fail” means that conformance test find the defect successfully.

12. Conclusion • This paper present an efficient and fully-automatic approach for conformance evaluation of SystemC designs. • Present an optimized algorithm for the generation of conformance tests. • An approach to automatically generate SystemC test benchs. • The results show the computational effort is reduced by the optimizations and all relevant kinds of defects can be detected.

13. My Common • This experiment result is match the problem which this paper want to overcome. • The proposed method is useful and efficient for verifying the SystemC designs. • This paper use a lot of idea of the other paper.