Graphic Tool for Computer Chip Layout

1. Graphic Tool for Computer Chip Layout Laura McLane Saint Michael’s College Advisor: Joanna Ellis-Monaghan

2. Description of the Problem • Chips are made up of functional units and connecting wires. • The units must be connected in a way that minimizes the distance between them in order to increase speed on the chip. • The difficulty of this problem comes from the vast number of units and wires needed to build each chip. • The challenge is to find a physical layout for the chip. Hudson River, 2003

3. Constraints • Functional units may not overlap. • Wires may only lie horizontally or vertically on the chip. • Each layer of the chip contains wires moving only in one direction. Hudson River, 2003

4. The Wiring Space Placement layer-gates/pins go here Vias (vertical connectors) Horizontal wiring layer Up to 12 or so layers Vertical wiring layer Hudson River, 2003

5. B D G A F C E H Graphical Representation • The best way to minimize the congestion and number of layers needed on a chip is to minimize the number of times wires “cross” and the number of “bends” in each wire. ~John Cohn Hudson River, 2003

6. Real Life Congestion Examples Congested area What often happens What would be good Hudson River, 2003

7. Functional units are thought of as nodes with fixed area. The dimensions for each node may change, but the area must stay constant. The netlist contains all the following information in abstract form. Mathematical Representation Hudson River, 2003

8. Continued • Connections are edges between the nodes. • An edge is defined by the 2 nodes it connects, the width (representing number of connecting wires), and the maximum delay (length the wire may be). Hudson River, 2003

9. 2 1 5 6 8 7 4 3 1 5 6 7 8 4 3 Related Problem • Geometric thickness of a graph is the smallest number of layers such that we can draw the graph in the plane with straight line edges and assign each edge to a layer so that no two edges on the same layer cross.~Dillencourt, Eppstein, Hirschberg Upper Bound for K2j =j/2 2 Hudson River, 2003

10. K8 – 2 Layers Overlaid 2 1 5 6 8 7 4 3 Hudson River, 2003

11. Upper Bound • If the number of layers determined by the geometric thickness of a graph is n, then the upper bound on the number of layers possible with chip layout is 2n, not taking into account the area of the chip. This is the case because each line in a geometric thickness graph could be replaced by “steps” of horizontal and vertical lines on the chip. Hudson River, 2003

12. Our Constraints are different • The graph will not resemble a geometric graph because we want to minimize the area of the layout. • However, It is possible to create a layout with less layers however, because the wires on a chip can “cross” by taking a series of horizontal and vertical paths instead of direct diagonal paths between nodes. Hudson River, 2003

13. K8 – Chip Layout Hudson River, 2003

14. My Graphical Tool Hudson River, 2003

15. Edge Length and Overlapping Hudson River, 2003

16. Overlap Hudson River, 2003

17. Automatic Spacing Hudson River, 2003

18. Conclusion • Further research is being done to come up with a better way to partition the netlist of units into larger blocks, and also to find a way of minimizing the distance wires cover to connect units, while avoiding congestion. Hudson River, 2003