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Real World FPGA design with Verilog. Milo š Milovanović miloshm@yahoo.com Jovan Popović josars@galeb.etf.bg.ac.yu Veljko Milutinović vm@etf.bg.ac.yu. Literature. - Real World FPGA Design with Verilog by Ken Coffman, Prentice Hall PTR - On-line Verilog HDL Quick Reference Guide
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Real World FPGA design with Verilog Miloš Milovanović miloshm@yahoo.com Jovan Popović josars@galeb.etf.bg.ac.yu Veljko Milutinović vm@etf.bg.ac.yu
Literature - Real World FPGA Design with Verilog by Ken Coffman, Prentice Hall PTR - On-line Verilog HDL Quick Reference Guide by Stuart Sutherland titan.etf.bg.ac.yu/~gvozden/VLSI/ Miloš Milovanović /75
Field Programmable Gate Array design • Verilog – designed as a simulation and test language • Real World - &¨!¸!!”#$%&@#$% Miloš Milovanović /75
A day in the life of anFPGA Silicon Designer Miloš Milovanović /75
Design must be: • Understandable to other designers • Logically correct • Perform under worst-case conditions of temperature and process variation Miloš Milovanović /75
Design must be: • Reliable • Testable and can be proven to meetthe specification • Do not exceed the power consumption goals (a battery-operated circuit) Miloš Milovanović /75
Understandable Design Miloš Milovanović /75
FPGA Architecture Miloš Milovanović /75
Xilinx 4K Family CLB Architecture Miloš Milovanović /75
Trivial Overheat Detector Example josars@galeb.etf.bg.ac.yu “Big Brother” vm@etf.bg.ac.yu Miloš Milovanović /75
Solution: Miloš Milovanović /75
Simulation Miloš Milovanović /75
Concurrent Initial: A=B=C=E=1 A <= B + C; D <= A + E; After assignment: A=2, D=2 Sequential Initial: A=B=C=E=1 A = B + C; D = A + E; After assignment: A=2, D=3 Assignments Miloš Milovanović /75
module module_name(port_name,port_name, ... ); module_items endmodule module module_name (.port_name (signal_name ), .port_name (signal_name ), ... ); module_items endmodule Module – the building block Miloš Milovanović /75
Module Port Declarations port_direction[port_size]port_name, port_name, ... ; port_direction – input, output, inout port_size is a range from [ msb: lsb] Example1: Example2: parameter word = 32;input [15:12] addr; input [word-1:0] addr; Miloš Milovanović /75
Data Type Declarations 1 register_type[size] variable_name, variable_name, ...; register_type[size] memory_name[array_size]; register_type: reg - unsigned variable of any bit size integer - signed 32-bit variable time- unsigned 64-bit variable real or realtime - double-precision floating point variable Miloš Milovanović /75
Data Type Declarations 2 net_type[size] #(delay) net_name, net_name, ...; net_type: wire or tri - Simple Interconnecting Wire wor or trior - Wired outputs OR together wand or triand - Wired outputs AND together Miloš Milovanović /75
Data Type Declarations 3 #delay or #(delay) - Single delay for all output transitions #(delay,delay) - Separate delays for (rising, falling) transitions Miloš Milovanović /75
Data Type Declarations 4 • wire a, b, c; • tri [7:0] data_bus; • reg [1:8] result; // an 8-bit //unsigned variable • reg [7:0] RAM [0:1023]; 8-bits wide, with 1K of addresses • wire #(2.4,1.8) carry;a net with rise, fall delays Miloš Milovanović /75
Assign statement • Continuous (combinational) logic - net_type[size]net_name;assign #(delay)net_name=expression; - net_type[size]net_name=expression; assign out = in1 & in2; assign bidir = OE ? out : 1’bz; Miloš Milovanović /75
Procedural Blocks type_of_block @(sensitivity_list) statement_group: group_namelocal_variable_declarations timing_controlprocedural_statementsend_of_statement_group Miloš Milovanović /75
Type of block • initial– processstatements one time • always– processstatementsrepeatedly Miloš Milovanović /75
Sensitivity list • OPTIONAL • Signals • Posedge – rising-edge triggered • Negedge – falling-edge triggered example: always @ (posedge clk or posedge rst) begin … end Miloš Milovanović /75
Statement group • begin – end – the sequential block • fork – join – statements are evaluated concurrently Miloš Milovanović /75
Example initial fork #10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA; join Miloš Milovanović /75
Example always begin #10 bus = 16'h0000; #20 bus = 16'hC5A5; #30 bus = 16'hFFAA; end Miloš Milovanović /75
Example 1 Miloš Milovanović /75
Verilog Hierarchy module_name instance_name(port_list); Miloš Milovanović /75
Named & Positional Assignment Miloš Milovanović /75
Built-in Logic Primitives • and, or, nand, nor, xor, nxor • bufif0, bufif1, notif0, notif1 Miloš Milovanović /75
Latches and Flipflops • Clocked D flipflop Miloš Milovanović /75
Basic Latch Miloš Milovanović /75
test_out2 <= 0; Miloš Milovanović /75
Blocking and Nonblocking Assignments Miloš Milovanović /75
Blocking assignmentsare order sensitive Miloš Milovanović /75
Nonblocking Assignment Miloš Milovanović /75
Miscellaneous Verilog Syntax Items • Numbers • default: 32 bits wide • size’base value • underscore is legal • X is undefined • Z is the high impedance Miloš Milovanović /75
Number examples Miloš Milovanović /75
Forms of Negation • ! – logical negation • ~ - bitwise negation Miloš Milovanović /75
Forms of AND • & is a bitwise AND • && is a logical AND (true/false) Miloš Milovanović /75
Forms of OR • | is a bitwise OR • || is a logical OR (true/false) Miloš Milovanović /75
AND/OR examlpe Miloš Milovanović /75
Equality Operators • == is logical equality have an unknown (x) result if any of the compared bits are x or z • === is case equality looks for exact match of bits including x’s and z’s and return only true or false Miloš Milovanović /75
Not equal operators • !=opposite to == • !== opposite to === Miloš Milovanović /75
