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Impact of Guardband Reduction on Design Process Outcomes

This study examines the influence of reducing guardbands on design process outcomes at UC San Diego, evaluating the impact on yield and discussing the benefits of Design for Manufacturing (DFM) techniques. Various factors affecting the manufacturing process and decisions related to guardband reduction are explored.

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Impact of Guardband Reduction on Design Process Outcomes

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  1. Impact of Guardband Reduction on Design Process Outcomes Kwangok Jeong (kjeong@vlsicad.ucsd.edu) Andrew B. Kahng (abk@cs.ucsd.edu) Kambiz Samadi (kambiz@vlsicad.ucsd.edu) University of California, San Diego

  2. Outline • Motivation • Background • Model Guardband Reduction • Design Flow & Test Cases • Experimental Results • Discussion: Impact on Yield • Conclusion

  3. Which is the better process? 99% Yield 70% Yield Foundry 2 Foundry 1 Which is the better process? Failed chip Is High Yield ALWAYS Better? • High yield is a general target of IC manufacturing • But, more design effort and larger guardband are required to make a chip immune to process / environment variations

  4. How Much Benefit Comes From DFM? • Many techniques claim to reduce guardband by X%. • Gupta et. al (DAC ’04): 40% guardband reduction by adopting iso-dense variational timing analysis • Sylvester et. al (VLSITSA’99): 60% of BEOL guardband reduction • What is the value or cost of guardband? • Designer: Minimize guardband • Foundry: Maximize guardband • The impact of guardband on design process outcomes has never been quantified before. How to decide it?

  5. Outline • Motivations • Background • Model Guardband Reduction • Design Flow & Test Cases • Experimental Results • Discussion: Impact on Yield • Conclusion

  6. Mask CD Error Defocus/Dose Variation Misalignment Non-Rectangular Shapes Flare Erosion/Dishing in CMP Line-End Shortening Wafer flatness Line Edge Roughness Lens Aberration Non-Uniform CD Reliability Alpha-Particle Imperfect regulators Temperature Variation NBTI Electro-Migration IR-drop Hot-Carrier Injection Crosstalk FEOL (Front-End of Line) BEOL (Back-End of Line) Delay / Leakage Variation Capacitance/ Resistance Variation Why do we need guardband? • Cloud of uncertainties • Guardband should cover the uncertainties • High coverage of variations lead to high yield • Variability tolerance has been increased (cf. ITRS 2005)

  7. Setup critical Hold critical Setup critical  Increase cost  Increase cost Increased Area Slower @WC Increasing Guard- band Robust Timing Opt. Increased Runtime Faster @BC Guardband vs. Design Outcomes • Delay of the setup critical path must be fast at the worst corner Increasing drive strength of cells • Delay of the hold critical path must be slow at the best corner Inserting delay cells

  8. Outline • Motivations • Background • Model Guardband Reduction • Design Flow & Test Cases • Experimental Results • Discussion: Impact on Yield • Conclusion

  9. Traditional Guardband • Example of the guardband • We model the reduction of both FEOL and BEOL guardband

  10. Cell delay and Transition time: M x M table Function (Input slew, Output load) Input capacitance: 1 x 1 table Guard Band Reduction Reduce guardband evenly between best and worst corners pin(Z) { direction : output; max_capacitance : 0.0693; function : "(A1 A2)"; timing() { related_pin : "A1"; timing_sense : positive_unate; cell_rise(delay_template_7x7) { index_1 (“i1, i2, i3, i4, i5, i6, i7");// Input slew index_2 (“j1, j2, j3, j4, j5, j6, j7");// Output load values(“v11, v12, v13, v14, v15, v16, v17", \ “v21, v22, v23, v24, v25, v26, v27", \ “v31, v32, ...); } Valuebest Valueworst 0 Example: 40% guardband reduction Valuebest Valueworst 0 False derating using ‘k_factor’ FEOL Guardband: Liberty Model Scaling

  11. FEOL Guardband Reduction • Goal: Entry-by-Entry BC-WC Guardband Reduction Original Worst Original Best Inter/extra-polation w/ worst indices Index Matched Best Move toward best value Move toward worst value New Best New Worst

  12. BEOL Guardband: SOCEncounter • Resistance: worst case is 1.16X greater than best • Major parameter: Temperature • Capacitance: worst case is 1.11X greater than best • Major parameter: Process Resistance Comparison Capacitance Comparison Worst = Best * 1.16 Worst = Best * 1.11 Worst (125C, 0.9V) Worst (125C, 0.9V) Best (-40C, 1.1V) Best (-40C, 1.1V) * Using OSTRICH from CADENCE

  13. BEOL Guardband: Star-RCXT • Resistance: worst case is 1.17X greater than best • Major parameter: Temperature • Capacitance: worst case is 1.13X greater than best • Major parameter: Process Resistance Comparison Capacitance Comparison Worst = Best * 1.17 Worst = Best * 1.13 Worst (125C, 0.9V) Worst (125C, 0.9V) Best (-40C, 1.1V) Best (-40C, 1.1V) * Using Star-RCXT from SYNOPSYS

  14. BEOL Guardband Reduction

  15. Outline • Motivations • Background • Model Guardband Reduction • Design Flow & Test Cases • Experimental Results • Discussion: Impact on Yield • Conclusion

  16. Design Flow Cadence SOC Encounter Cadence RTL Compiler Timing Optimization Synthesis Synopsys DFT Compiler Yes Setup? Scan Insertion No Cadence SOC Encounter Cadence SOC Encounter Floorplan Routing Cadence SOC Encounter Placement Timing Optimization Cadence SOC Encounter Yes Setup Timing Optimization No Yes Setup? Yes Hold No Cadence SOC Encounter No CTS Signoff Synopsys STAR-RCXT, PrimeTime

  17. Testcases and Figures of Merit • Testcases • Metrics • Quality of Results • Area, # Instances, Wirelength, etc. • Design Cycle • Runtime, # violations, TNS, WNS, etc.

  18. Outline • Motivations • Background • Model Guardband Reduction • Design Flow & Test Cases • Experimental Results • Discussion: Impact on Yield • Conclusion

  19. FEOL Guardband is much larger than BEOL’s FEOL: Worst Case Delay ~ 2 x Best Case Delay BEOL: Worst Cap. ~ (1.11~1.13) x Best Cap. BEOL Guardband vs. FEOL Guardband (1) Valuebest Valueworst 0 100% 200% Example: 50% guardband reduction on FEOL Worst case delay will be reduced by about 25% Valuebest Valueworst 0 106% 100% Example: 50% guardband reduction on BEOL Worst case capacitance will be reduced by less than 2%

  20. Impact of Guardband Reduction • FEOL • Reducing guardband greatly affects the stage delay and the timing gap between best and worst • BEOL • Reducing guardband would not affect timing much • From these observations, we can conclude FEOL will have more impacts on design outcomes.

  21. Impact on Quality of Results (1): Area • 40% of GB Reduction BEOL only FEOL only FEOL+BEOL

  22. Impact on Quality of Results (2): Wirelength • 40% of GB Reduction BEOL only FEOL only FEOL+BEOL

  23. Impact on Design Cycle Time • Total design cycle time = f(runtime, iteration) • Iteration depends on the timing characteristics • # Violations • How many paths designer should concern • Total negative slack (TNS) • How much effort of timing optimization will be required • Worst negative slack (WNS) • Feasibility of timing convergence

  24. Impact on Design Cycle Time (1): Runtime BEOL only FEOL only FEOL+BEOL • 40% of GB Reduction

  25. Impact on Design Cycle Time (2): Violations BEOL only (90nm jpeg) FEOL only (90nm jpeg) (90nm Jpeg case) (90nm Jpegcase) • 40% of GB Reduction FEOL+BEOL (90nm jpeg) (90nm Jpeg case)

  26. Outline • Motivations • Background • Model Guardband Reduction • Design Flow & Test Cases • Experimental Results • Discussion: Impact on Yield • Conclusion

  27. Impact on Random Defect Yield • Overall yield is defined by • Random Defect Yield • Strong function of die area (A) Binomial Probabilistic Distribution Function for good die

  28. Impact on Parametric Yield • Parametric Yield vs. Guardband • Ys can be estimated by considering normal distribution with best case and worst case being set at -3σ and +3σ • For x% of guardband reduction, Ys is defined as, • For 0% guardband reduction: Ys=0.9973 • For 40% guardband reduction: Ys=0.9281 about 7% yield loss

  29. Impact on Yield: Scenario 1 • Scenario1: Parametric yield is constant • Adopting manufacturing-aware techniques (i.e., iso-dense timing analysis, better process equipments, etc.) foundries can reduce design guardband • 40% guardband reduction results in 10% increase in total number of good dies @ α=Inf., d=0.2/um^2, 300mm wafer

  30. Impact on Yield: Scenario 2 • Scenario 2: Guardband reduction in design process (Actual guardband of fabrication is unchanged) • Parametric yield will decrease • Random defect yield will increase • 20%guardband reduction results in4%increase in total number of good dies per wafer

  31. Conclusions • We quantify impact of guardband reduction • Typical outcome: 13%,12% and 28% reductions in standard-cell area, total wirelength and SP&R runtime metrics from 40% reduction in library model guardband • 100% reduction in number of timing violations for a netlist that is synthesized with original library and extraction guardbands  this improvement can be very significant in improving timing closure and design cycle turnaround time • 4% increase in the number of good dies per wafer by 20% artificial reduction from 3sigma guardband • Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices

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