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Chapter 8

Chapter 8. Overview Programmed I/O Introduction to Interrupt Driven I/O Project 3. Digressing. How do you do the following in the LC-3 ? (good test question ?) Shift left Rotate left Shift right Rotate right. Input / Output.

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Chapter 8

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  1. Chapter 8 • Overview • Programmed I/O • Introduction toInterrupt Driven I/O • Project 3

  2. Digressing How do you do the following in the LC-3 ? (good test question ?) • Shift left • Rotate left • Shift right • Rotate right

  3. Input / Output Memory Mapped I/O – A section of the memory address space is reserved for I/O Registers rather than general memory locations. Think of it as “pseudo” memory. The same instructions are used for general programming and I/O programming. Non-Memory Mapped I/O – There is a separate address space for I/O programming, and an entirely separate set of I/O Instructions.

  4. LC-3 has Memory Mapped I/O LC-3 Memory Layout: x0000 – x00FF Trap vectors x0100 – x2FFF System Programs & Data x3000 – xFDFF User Programs Area xFE00 – xFFFF I/O Programming “Registers”

  5. LC-3 has Memory Mapped I/O LC-3 Memory Layout: x0000 – x00FF Trap vectors (Supports Software Interrupts) x0020 [x0400] GETC (Read Char from Keyboard) x0021 [x0430] OUT (Write Character to Console) x0022 [x0450] PUTS (Write string to Console) x0023 [x04A0] IN (Prompt, input character from Keyboard, echo character to Console) x0024 [x04E0] PUTSP (Write “packed” string to Console) x0025 [xFD70] HALT (Turn off run latch in MCR) x0100 – x01FF Interrupt Vectors (Supports Hardware Interrupts) x0200 – x2FFF System Programs & Data (“Operating System”) x3000 – xFDFF User Programs Area xFE00 – xFFFF I/O Programming “Registers” (Mapped I/O Regs) xFE00 KBSR [15 {Ready}, 14 {Intr enable}] (Keyboard Status Register) xFE02 KBDR [7:0{ascii data}] (Keyboard Data Register) xFE04 DSR [15{Done}, 14{Intr enable}] (Display Status Register) xFE06 DDR [7:0{ascii data}] (Display Data Register xFFFE MCR [15{Run latch}] (Machine Control Register)

  6. Synchronous vs Asynchronous I/O Synchronous – latest value of data could be expected to be available when the program wanted it. It might be periodically updated at a know frequency. This is not typical nor usually realistic for I/O. Asynchronous – computer is generally much faster than I/O so program must wait until requested data is available or data provided has been taken. “Handshaking” is used to ensure that data is available or I/O device is ready.

  7. Polling vs Interrrupt Driven I/O Polling – program checks handshaking signals to find when data is available of device is done (typically a loop in the program) Interrupt – program initiates I/O and waits until data is available (typically goes to sleep until the operating system wakes the program up)

  8. Keyboard Input Interface

  9. Keyboard Input Registers KBDR (Keyboard Data Register): Assigned to xFE02 Data is in KBDR[7:0] Read only Register KBSR (Keyboard Status Register): Assigned to xFE00 Status “ready” is KBSR[15] Set to “1” when new data is ready Cleared when data is read

  10. Simple Program for Input from Keyboard ; Waiting for a character to be entered START LDI R1, KBSR ; Test for character input BRzp START ; If not there, try again LDI R0, KBDR ; Read character BRnzp NEXT_TASK ; Go to the next task KBSR .FILL xFE00 ; Address of KBSR (Keyboard Status Register) KBDR .FILL xFE02 ; Address of KBDR (Keyboard Data Register)

  11. Console Output Interface

  12. Console (Monitor) Output Registers DDR (Data Direction Register): Assigned to Address xFE06 Data is in DDR[7:0] DSR (Data Data Register): Assigned to Address xFE04 Status “done” bit is DSR[15] Set to “1” when data is picked up Cleared when new data is written

  13. Simple Program to Output to Console (Monitor) ; Wait for write to Console done START LDI R1, DSR ; Test for output written BRzp START ; If not, try again STI R0, DDR ; Write character BRnzp NEXT_TASK ; Go to next task DSR .FILL xFE04 ; Address of DSR (Display Status Register) DDR .FILL xFE06 ; Address of DDR (Display Data Register)

  14. LC-3 Memory Mapped I/O

  15. Echo from Keyboard to Monitor ; Echo keyboard input to Console output START LDI R1, KBSR ; Test for input ready BRzp START LDI R0, KBDR ECHO LDI R1, DSR ; Test for output done BRzp ECHO STI R0, DDR BRnzp NEXT_TASK KBSR .FILL xFE00 ; Address of KBSR KBDR .FILL xFE02 ; Address of KBDR DSR .FILL xFE04 ; Address of DSR DDR .FILL xFE06 ; Address of DDR

  16. The I/O Routine to Echo a Line of Input .orig x3000 ; Program to read and echo line from the Console ST R1, SaveR1 ; Save registers needed ST R2, SaveR2 ; by this routine ST R3, SaveR3 LD R2, Newline ; Store newline Character in R2 L1 LDI R3, DSR ; Loop until Monitor is done BRzp L1 STI R2, DDR ; Move cursor to new clean line LEA R1, Prompt ; Load starting address of prompt string Loop LDR R0, R1, #0 ; Get prompt character BRz Input ; Branch to Loop on null (0) L2 LDI R3, DSR ; Loop until Monitor is done BRzp L2 STI R0, DDR ; Write prompt character ADD R1, R1, #1 ; Increment Prompt pointer BRnzp Loop ; Go to get next prompt character

  17. The I/O Routine to Echo a Line of Input (2) Input LDI R3, KBSR ; Poll until a character is typed BRzp Input LDI R0, KBDR ; Get input character L3 LDI R3, DSR ; Loop until Monitor is done BRzp L3 STI R0, DDR ; Echo input character ADD R0, R0, #-10 ; Test for newline (done) BRnp Input ; Loop if not done L4 LDI R3, DSR ; Loop until Monitor is done BRzp L4 STI R2, DDR ; Move cursor to new clean line LD R1, SaveR1 ; Restore registers LD R2, SaveR2 ; to original values LD R3, SaveR3 BRnzp NEXT_TASK ; Do the program's next task

  18. The I/O Routine to Echo a Line of Input (3) SaveR1 .BLKW 1 ; Memory for registers saved SaveR2 .BLKW 1 SaveR3 .BLKW 1 DSR .FILL xFE04 DDR .FILL xFE06 KBSR .FILL xFE00 KBDR .FILL xFE02 Newline .FILL x000A ; ASCII code for newline Prompt .STRINGZ "Input character line> " NEXT_TASK BRnzp NEXT_TASK ; Simulates next task .END Run on Simulator

  19. I/O Interrupts Requirements for a device to interrupt the processor • The device must have the right to request service • The I/O device must want service • The device request must be at a higher priority than what is being done by the processor or is being requested by other devices • The processor must be completed with the present instruction execution

  20. Device(s) Generating Interrupt Request

  21. Generating the LC-3 Interrupt Request

  22. Servicing an Interrupt The following process is followed to service an interrupt • The CPU enters the Supervisor State • The “context” of the present program is saved (PC, PSW, SP) • The device provides the address of location in the interrupt service routine table where the pointer to the service routine should reside. • The Supervisor loads the address of the service routine into the PC • The service routine is executed (ending with an RTI) • The context of the original program is loaded and the original program resumed

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