1 / 46

LatticeMico32

LatticeMico32. Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS. LatticeMico32. Agenda Architecture and Peripherals Development tools Software Deployment Tool Flow Demo. Introducing the LatticeMico32. Flexible, High Performance 32-Bit Microprocessor

trapper
Download Presentation

LatticeMico32

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. LatticeMico32 Technical Seminar Tour 2007 LATTICE‘S PROGRAMMABLE LOWCOST SOLUTIONS

  2. LatticeMico32 Agenda • Architecture and Peripherals • Development tools • Software Deployment • Tool Flow • Demo

  3. Introducing the LatticeMico32 • Flexible, High Performance 32-Bit Microprocessor • Optimized For Lattice Leading-Edge Families • LatticeEC/P • LatticeECP2/M • LatticeSC • LatticeXP • Targeted Towards Wide Variety of Applications • Consumer • Computation • Communications • Medical • Industrial • Automotive

  4. Performance Enhanced Feature Set • RISC architecture • 32-bit data path and 32-bit instructions • 32 general purpose register • Handles up to 32 external interrupts • Optional instruction and data caches • Dual Wishbone memory interfaces(Instruction and Data)

  5. Architecture

  6. Architecture and Pipeline Stages

  7. Peripheral Components • Enable Design of Complete Embedded Systems • Connect via a WISHBONE Bus Interface • Royalty-free • Public domain specification controlled by OpenCores.org

  8. Peripheral Components • Broad Selection • Coming from Lattice • Asynchronous SRAM Controller • On-Chip Memory Controller • 32-bit Timer • DMA Controller • GPIO • I2C Master Controller • SPI • UART • DDR ($) • OpenCores.org • There is a real documentation coming from Latticehow to create and add wishbone-compatible componentsto the LatticeMico32 development system!!!! Connectivity With a Click Using Design Tools

  9. FPGAConfig Complete Embedded System FPGA Flash/ RAM Embedded RAM User Logic LatticeMico32 Processor Core Interrupt Lines 32-bitTimer SRAMController WISHBONE On-ChipMemory UART GPIO Flash MemoryController

  10. Support Timetable By Device Family • Schedule for Family Support: • LatticeEC/ECP/ECP2/M Now • LatticeSC November 2006 • LatticeXP January 2007

  11. Resource Utilization & Performance

  12. Open IP Core Licensing • Innovative Open IP Core License • Visibility, Reliability, Scalability • Free of Charge • Generated LatticeMico32 core and Peripherals based on HDL

  13. Development Tool LatticeMico32 System • to implement HW-IP (uP and Peripherals) and SW • Based on Eclipse C/C++ Dev. Tools (CDT) • Free of charge, via Internet • Combined with ispLEVER

  14. Development Tool LatticeMico32 System • Mico System Builder (MSB) • Generate uP platform and HDL • Choose peripherals • Specify connectivity between peripherlas • C/C++ SW Projekt Environment (SPE) and Debugger • Eclipse development environment • GNU-based compiler, linker, assembler, debugger

  15. RTOS Support Micrium’s uC/OS-II RTOS • Included in LatticeMico32 System • Open source • free of charge for eval and non-commercial use • For commercial-use obtain a license directly from Micrium

  16. Software Deployment Deploying to • External Parallel Flash • On-Chip (Embedded Block RAM EBR)

  17. FPGA Parallel Flash FPGA Config Flash SPI JTAG UART OnChip Mem (EBR) User Logic BIT SRAM / DDR LatticeMico32 System PC (Debugger, ispVM) BIT ELF Software Deployment:External #1 • Load app.design toFPGA config flash • FPGA configurationvia SPI

  18. FPGA Parallel Flash FPGA Config Flash SPI JTAG UART OnChip Mem (EBR) User Logic BIT SRAM / DDR LatticeMico32 System PC (Debugger, ispVM) BIT ELF ELF Software Deployment: External #2 • multipleLoad app.code to RAM • Run app.code from RAM • debugging

  19. FPGA Parallel Flash FPGA Config Flash SPI User Logic JTAG UART OnChip Mem (EBR) BIT SRAM / DDR LatticeMico32 System PC (Debugger, ispVM) BIT ELF Flash Programmer Flash Programmer Software Deployment: External #3 • Load FlashProgrammerto RAM • Run FlashProgrammerfrom RAM

  20. FPGA Parallel Flash FPGA Config Flash SPI User Logic JTAG UART OnChip Mem (EBR) BIT SRAM / DDR LatticeMico32 System PC (Debugger, ispVM) BIT ELF ELF Flash Programmer Flash Programmer Software Deployment: External #4 • FlashProgrammercopies app.code toParallelFlash

  21. FPGA JTAG UART OnChip Mem (EBR) User Logic BIT LatticeMico32 System ELF ELF Software Deployment: External #5 • Copy app.code toRAM • Run app.code fromRAM Parallel Flash FPGA Config Flash SPI SRAM / DDR

  22. FPGA FPGA Config Flash SPI JTAG UART OnChip Mem (EBR) User Logic BIT LatticeMico32 System PC (Debugger, ispVM) BIT ELF Software Deployment:OnChip #1 • Load app.design toFPGA config flash • FPGA configurationvia SPI

  23. FPGA FPGA Config Flash SPI JTAG UART OnChip Mem (EBR) User Logic BIT LatticeMico32 System PC (Debugger, ispVM) BIT ELF ELF Software Deployment: OnChip #2 • multipleLoad app.code to EBR • Run app.code from EBR • debugging

  24. FPGA FPGA Config Flash SPI JTAG UART OnChip Mem (EBR) User Logic BIT LatticeMico32 System PC (Debugger, ispVM) BIT ELF Software Deployment:OnChip #3 • Resynthesize FPGAbitstream • Load app.design toFPGA config flash • FPGA configurationvia SPI

  25. Software Deployment: This are just very simplified descriptions Please have a look to: • LatticeMico32 Tutorial(based on the Lattice32 Development Board) • SW Developers UserGuide

  26. Development Board LatticeECP 33 + SPI DDR SODIMM socket 2x128 Mbit Flash + 2x4 Mbit SRAM USB 2.0 Connector for programming Flywire Connector for programming 9-pin RS232 serial port 15-pin VGA connector for 64 colors Ethernet 10/100 M full/half duplex Multiple USB connectors Sigma Delta D/A converter Audio interface (line-in and line-out) LCD connector for character displays 25 MHz oscillator Two-character 7-segment display Power Supply, USB Cable 595 $ ECP Development

  27. Software Deployment Deploying to • External Parallel Flash Memory • Embedded Block RAM (EBR) Alternatives: • External Parallel Flash Memory = ConfigFlash(needs a small CPLD) • External SPI Flash(coming soon)

  28. System Development Flow Platform Development Software Development HW Platform C/C++ Software Project Environment (SPE) and Debugger Mico System Builder (MSB) .h Generator Instruction Set Simulator HDL ELF Debug FPGA DesignImplementation Rest of User Design in HDL Debug ispVM™ Program Target Board

  29. System Development Flow Restriction: (not really ;-) • MSB delivers Verilog • But ispLEVER does not support mixed language designs • Do you speak Verilog ?? • -> use NGO-Flow • How?? Ask your AVM-FAE

  30. LatticeMico32 Tool Flow • Create New project, • Verilog HDL, • part type ECP33-3F484C if Mico32 dev board is used

  31. Tool Flow • Invoke Mico32 from IspLever

  32. Tool Flow • Create a Platform: • Platform is processor + peripherals • Pre-defined Platforms or create your own • Platforms A-E match the LatticeMico32 development board

  33. Tool Flow • Configure Platform • Configurations (e.g. Peripheral name, Wishbone connections, Memory location, size, interrupts, etc) are specified here

  34. Tool Flow • Configure processor or peripheral: • Double click instance name, and configuration options appear

  35. Tool Flow • Generate Platform • Addresses, Irq, DRC, Generate HDL

  36. LatticeMico32 Tool Flow • Importing an LM32 Project • <path>/<project>/soc/<project>.v

  37. Tool Flow • Importing Development board constraints • “Source” “import constraint/preference file” • <isptools6.1>/micosystem/platforms/platformxy • Pinouts for SRAM, LED’s, etc.

  38. Tool Flow • Change Perspective from ‘MSB’ to “C/C++”

  39. Tool Flow • Using the SPE Environment • ‘New “Mico32 New Managed C project”

  40. Tool Flow • Using the SPE Environment • Select a template

  41. Tool Flow • Using the SPE Environment • Compile C Code • Make utility will compile source • Check for errors

  42. Tool Flow • Using the SPE Environment • Execute C Code • Select ‘Run’ ‘debug – mico32 hardware’ • The demo board can now be executed

  43. LatticeMico32 Website http://www.latticesemi.com/products/intellectualproperty/ipcores/latticemico32.cfm

  44. LatticeMico32 Processor Reference Manual LatticeMico32 Software Developer User's Guide LatticeMico32 Development Kit User's Guide LatticeMico32 Tutorial Online Help Workbench MSB C++ Debug Sparkle Sheet LatticeMico32 System Installation Guide Creating Components in the LatticeMico32 System Peripheral Component Data Sheets and Help Panels DMA Controller GPIO I2C Master from OpenCores On-Chip Memory Controller SPI Asynchronous SRAM Controller Parallel Flash Controller 32-bit Timer UART Detailed LatticeMico32 Documentation

  45. Recommendation: LatticeMico32 Tutorial • ~ 3 Hours for completion • Based on LatticeMico32 Dev. Board

  46. Development Board LatticeECP 33 + SPI DDR SODIMM socket 2x128 Mbit Flash + 2x4 Mbit SRAM USB 2.0 Connector for programming Flywire Connector for programming 9-pin RS232 serial port 15-pin VGA connector for 64 colors Ethernet 10/100 M full/half duplex Multiple USB connectors Sigma Delta D/A converter Audio interface (line-in and line-out) LCD connector for character displays 25 MHz oscillator Two-character 7-segment display Power Supply USB Cable 595$ Development Board

More Related