Timing Model Reduction for Hierarchical Timing Analysis

1. Timing Model Reduction for Hierarchical Timing Analysis Shuo Zhou Synopsys November 7, 2006

2. Outline • Static Timing Analysis in Design Flow • Hierarchical timing analysis • Proposed Techniques • Iterative timing model reduction algorithm based on a biclique-star replacement technique. • Experimental Results • Conclusions

3. Design Flow Floorplaning Static Timing Synthesis Analysis Placement &Routing Static Timing Analysis in Design Flow • Static Timer is integrated in each stage. • Need efficient static timer.

4. Hierarchical Timing Analysis • Hierarchical timing analysis is essential for hierarchical design. • Consider circuits inside the blocks to be fixed. • Complexity O(n): n is #edges in timing models. gates gates gates Partition Design into Blocks Characterize Blocks into Timing Models

5. Problem Statement • Timing model minimization for hierarchical timing analysis: • Given a hierarchical block, construct an abstract timing model with minimal number of edges that covers the longest and shortest path delays of each pair of input and output in the block.

6. Previous Works • Transform timing graph [Visweswariah ICCAD’99, Moon DAC’02]. • Perform serial/parallel edge merging. • Represent delay matrix with minimal number of edges. • Optimal realization of a distance matrix [Hakimi Quart. Appl. Math. 22 (1964), Chung http://www.math.ucsd.edu/˜fan]. • Biclique-star replacement for bicliques with unit edge delay [Feder Symp. on Theoretical Aspects of Computer Science (2003)].

7. Terminologies: Bipartite Timing Model • G = {B, D, E} • Input set B, output set D, and edge set E • Longest and shortest delays.

8. Bipartite timing model 3 1 9 7 8 6 Timing graph 2 10 7 1 2 4 1 9 4 1 5 1 11 3 2 2 1 10 5 7 2 2 1 1 1 1 3 6 11 8 3 path: 1->4->5->7->8->10

9. Bipartite timing model 3 1 4 7 Outputs Delay matrix 8 O4 O5 O6 6 2 5 7 I1 3 7 8 4 Inputs ¥ I2 6 7 5 6 3 ¥ 4 I3 5 Delay matrix • Element on row i col j is delay from input i to output j,  for disconnected input i and output j. • Row i implies input delay vector = {di,j| di,j from input i.}

10. Star 4 1 4 1 3 3 s 2 5 4 1 3 6 Star • Gs = (Bs, Ds, s, Es) • Bs input set, Ds output set, center vertex s. • Edges (i,s) and (s,j).

11. Biclique-Star Replacement • Basic idea: match various input delay vectors to a pattern and cover each input delay vector by one edge plus the pattern.

12. Replace dij = dis+dsj Outputs Outputs O4 O5 O6 O4 O5 O6 Pattern I1 2 3 4 0 + 2 3 4 Input vectors = I2 3 4 5 1 + 2 3 4 I3 4 5 6 2 + 2 3 4 Biclique #edge = 9 star #edge = 6 2 1 4 4 1 3 0 2 4 3 3 1 4 s 5 2 5 2 5 4 2 4 5 6 3 6 6 3

13. Biclique Search Repeat Reduction Ratio Evaluation ratio = #edges_covered/(r+c) Re-evaluation Reduction > 1 Biclique-star Replacement Bipartite Timing Model Reduction

14. O4 O5 O6 I1 2 3 4 I2 3 4 5 Sub(I2,I1) V (I2,I1)= 1 1 1 Delay Vector Subtraction • Input delay vector subtraction Sub(Ia, Ib) • Distance vector V(Ia,Ib) = {jIa,Ib =da,j – db,j| j [1..c]} • Input vectors Ia, Ib share a pattern if all jIa,Ibare equal.

15. Biclique Expansion for Replacements • Choose an input delay vector as the pattern vector. • Expand the biclique of the pattern vector by covering as many as possible input vectors. • Replace the biclique by a star. Biclique Expansion (G, Ia, Gc) • Add edges (a,j) to biclique Gc; • For each input vector Ii • Vector subtraction Sub(Ii,Ia); • If all jIi,Ia= 0Ii,Ia add edges (i, j) to Gc. Biclique-star Replacement (Gc,Ia,Gs) • Add inputs, outputs, center vertex s, and edges (i,s), (s,j) to Gs • da,s = 0, ds,j = Ia,j; • For each edge (i,s) in Gs • di,s = 0Ii,Ia;

16. #edge = 9 #edge = 8 2 1 4 1 4 3 I1 0 2 4 3 1 3 4 s 5 2 5 2 0I2,I1 4 5 5 4 5 4 7 6 3 6 3 7 step 1 step 2 O4 O5 O6 O4 O5 O6 I1 2 3 4 I1 2 3 4 I2 3 4 5 I3 4 5 7 Sub(I2,I1) Sub(I3,I1) V (I2,I1) = 1 1 1 2 2 3 V(I3,I1) = 0I2,I1 Replace

17. Biclique Star 2 1 4 1 4 3 0 2 4 3 s 5 5 4 2 4 5 7 6 3 6 3 7 Don’t Care Edge Don’t Care Edges • Edge (i,j) is a don’t care edge in a biclique star replacement if path delay di,s + ds,j< di,j. Replace

18. Biclique Expansion with Don’t Cares • Choice: try each  in distance vector as di,s. • For d3,s =  • di,j is covered if di,s + ds,j = di,j, i.e., j = . • di,j is a don’t care edge if j > . • Output j has to be removed if j < .

19. O4 O5 O6 1 4 I1 2 3 4 2 0 1 4 I3 4 5 7 0 2 3 s 5 3 s 5 4 2 2 3 V(I3,I1) = 4 3 2 6 3 6 3 #edges covered decreases by 1 #edges covered increases by 2

20. Biclique Expansion and Replacement with Don’t Cares Biclique Expansion with Don’t Cares (G, Ia, Gc) • Add edges (a,j) to Gc; • For each input vector Ii • Vector subtraction Sub(Ii,Ip); • For each j in the distance vector For each k in distance vector if k = j #covered++; else if k < j #removed +=edges to output k; • If maximum (#covered - #removed of j )> 1; For each k in distance vector if kj Add edge (i,k) to Gc; else remove output k and edges to k. Replacement with Don’t Cares (Gc, Ia, Gs) • Add inputs, outputs, center vertex s, and edges to Gs • da,s = 0, ds,j = Ia,j; • For each edge (i,s) in Gs • di,s = min(Ii,Ia ).

21. #edge = 9 #edge = 7 2 1 4 1 4 3 0 2 4 3 1 3 s 5 2 4 5 2 4 2 5 4 Min I1 5 6 3 7 7 6 3 Don’t Care Edge step 1 step 2 O4 O5 O6 O4 O5 O6 I1 2 3 4 I1 2 3 4 I3 4 5 7 I2 3 4 5 Sub(I3,I1) Sub(I2,I1) 2 2 3 V(I3,I1) = V (I2,I1)= 1 1 1 Replace

22. Biclique Search Star Graph to Bipartite Graph Reduction Ratio Evaluation ratio = #edges_covered/(r+c) Re-evaluation Reduction > 1 Biclique-star Replacement Bipartite Timing Model Reduction

23. bipartite graph s1 1 s2 star timing model 2 1 5 9 3 s1 6 2 8 s2 4 7 3 s2' 7 8 4 s1' 5 9 Star Graph to Bipartite Graph Transformation Split s1,s2 Recover Stars 6

24. Correctness • G: the bipartite timing model before the reduction. • G': the timing model after the reduction. Edge delay di,j of any connected input i and output j in G is covered by the longest path delay di,j' from input i to output j in G' after the reduction.

25. Experimental Results • Test cases • Block 1: 8499 inputs, 16885 outputs, and 138,360 edges • Block 2: 4260 inputs, 7728 outputs and 103,414 edges • EG-- #edges in original timing graph of the block. • EB--#edges in bipartite timing model. • Em--#edges after timing model reduction. • Reduction rG = (EG – Em)/ EG. • Reduction rB = (EB – Em)/ EB.

26. |di,j – di,j’| <= Err_bound, where di,j and di,j’ are delays from input i to output j before and after the reduction. Buffer1 delay = 1.34ns.

27. Buffer 1 delay = 0.74ns.

28. Conclusions • We propose a biclique-star replacement technique and develop an iterative timing model reduction algorithm based the proposed technique. • By allowing reasonable error bounds, the experimental results show that the proposed algorithm can effectively reduce the number of edges in the timing model.

29. Thanks!

30. References • C.W. Moon, H.~Kriplani, and K.~P. Belkhale, “Timing model extraction of hierarchical blocks by graph reduction”, in DAC’02, 152-157. • C. Visweswariah and A.R. Conn, “Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation”, in ICCAD’99, 244-251. • S. L. Hakimi and S. S. Yau. “Distance matrix of a graph and its realizability.” Quart. Appl. Math. 22 (1964), 305–317. • F. Chung, M. Garrett, R. Graham, and D. Shallcross. “Distance realization problems with applications to internet tomography.” http://www.math.ucsd.edu/˜fan. • T. Feder and A. Meyerson and R. Motwani and L. O' Callaghan and R. Panigrahy, “Representing graph metrics with fewest edges.” in Proc. of Symp. on Theoretical Aspects of Computer Science (2003), 355--366.