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SVEN Scalable Video Engine Gerald Krottendorfer

SVEN Scalable Video Engine Gerald Krottendorfer. SVEN – Decoder/Encoder. SVEN – S calable V ideo En gine Video Decoder/Encoder. Fully programmable: multistandard / multiformat: MPEG-2 MPEG-4 H.264 WMV9/VC-1. Architecture. SVEN Architecture. SVEN. SVEN Architecture.

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SVEN Scalable Video Engine Gerald Krottendorfer

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  1. SVENScalable Video EngineGerald Krottendorfer

  2. SVEN – Decoder/Encoder SVEN – Scalable Video Engine Video Decoder/Encoder Fully programmable: multistandard / multiformat: MPEG-2 MPEG-4 H.264 WMV9/VC-1

  3. Architecture

  4. SVEN Architecture

  5. SVEN SVEN Architecture

  6. Video Processor SVEN

  7. Stream Processor SVEN

  8. Memory Controller SVEN

  9. Programmable Processingpower Scalability Bandwidth Video Decoder/Encoder: • Programmable • Processing Power • Bandwidth • Scalability Requirements

  10. Programmable • Multi standard compliancy:H.264 VC-1 MPEG-2 MPEG4 DIVx etc. … • High complexity of application Standard compliancy tests after TO Minimize design risks & time to market • Increased flexibility Programmable Processing power Scalability Bandwidth

  11. Processing Power • Enhanced compression standards: H.264, VC-1: higher compression rates at substantially higher processing power requirements High processing power requirements Programmable Processing power Scalability Bandwidth • In combination with High Definition Digital TV Standards: VERY high processing power needs

  12. Decoder + Encoder H.264 Decoder + Image processing MPEG-4 MPEG-2 Decoder Scalable Processor Programmable Processing power Scalability Processing Power Bandwidth decoding standard application

  13. Power & Core Size • Power and Area Scales with Processing power requirements Programmable Processing power Scalability Bandwidth

  14. Bandwidth Requirements H.264 DRAM Programmable 20 Mbit/s 490MB/s Processing power Bitstream Decoder 94MB/s Memory Controller 94MB/s Scalability 220MB/s 250MB/s Bandwidth 94MB/s IQ + IITrans Inter/intra prediction Deblocking 94MB/s Parameter • H.264 ... VERY High Databandwidth Needs

  15. Programmable Processingpower Scalability Bandwidth Video Decoder/Encoder: • Programmable • Processing Power • Bandwidth • Scalability Solution

  16. Dual Core Solution Dual Core Architecture: VIDEO Processor: • Transform operation • inter / intra prediction • filtering • Datapath: MAC (DSP) Programmable Control Processor Controller Processing power Video Processor Number Cruncher Scalability Bandwidth Control Processor: • stream parsing • data flow control • HW accelerator • Datapath: ALU (RISC)

  17. SVEN Film 1080i/720p Main Profile HDTV enhanced DTV Standard DSP Performance Limit D1 720x486 Baseline profile TI C64 dual Blackfin ADI Blackfin Embedded DSP Performance Limit CIF 352x288 Baseline Equator SVEN Performance Programmable SVEN Processing power Scalability Processing Power H.264 Decoder / picture format Bandwidth

  18. Linear Scalability SVEN versus DSP: Scalability Programmable Processing power Scalability Bandwidth --- Scalable Architecture ---DSP

  19. Cross Matrix Streamline Bus REG REG REG Broadcast Bus SLICE N SLICE 1 SLICE 0 Bandwidth • Data Transport in between Slices/Slots does not steal processing performance Processing Power Programmable • Flexible data exchange in between Slices due to cross matrix Processing power Scalability Bandwidth

  20. DATA_MEM DATA_MEM DATA_MEM SLOT 0 SLOT N SLOT 1 I/O Capabilities • Stream Processor: Each Slot has its own Data memory Programmable Processing power Scalability Bandwidth

  21. DATA_MEM A DATA_MEM B DATA_MEM A DATA_MEM A DATA_MEM B DATA_MEM B SLICE 0 SLICE N SLICE 1 I/O Capabilities • Stream Processor: Each Slot has its own Data memory Programmable • Video Processor: Each Slice has its own Data memories Processing power Scalability Bandwidth

  22. DMA ENGINE DATA_MEM A DATA_MEM B DATA_MEM A DATA_MEM A DATA_MEM B DATA_MEM B DMA IF SLICE 0 SLICE N SLICE 1 DMA Access • Stream Processor: Each Slot has its own Data memory Programmable • Video Processor: Each Slice has its own 2 Data memories Processing power Scalability • Direct Access to Video Buffer from all Slices via DMA port at each Slice Data Memory Bandwidth

  23. Scalable Bandwidth • Stream Processor: Each Slot has its one Data memory Programmable • Video Processor: Each Slice has its one 2 Data memories Processing power Scalability • Direct Access to Video Buffer from all Slices via DMA port at each Slice Data Memory Bandwidth Scalable Data Bandwidth

  24. 2004 2003 2005 2006 Roadmap • MPEG4 • DivX • MJPEG • JPEG2000 • etc... • VC-1 • H.264 • MPEG2 Library / Applications IP-Core • IP core • shipping • SVEN IP • Proof of concept: • Manufactured IC • VSP S8-32 • Proof of concept: • Manufactured IC • SVEN IP available • VSP IP available

  25. Controller-Debugger SVEN-Debugger Programming Toolchain • Eclipse based IDE • Simulator / Debugger • Assembler / C-Style Code • Compiler • Allows integration of external Processor cores (Host, Audio DSP)

  26. Case Study

  27. Multistandard HDTV Decoder Requirements: • Multistandard Decoder MPEG2 H.264 VC-1 • HDTV compliant 1080i60 … 30 fps 720p60 … 60fps

  28. Core Size & Power Technology: 130nm TSMC Clockspeed: 200MHz

  29. Summary • Fully Programmable All video formats: H.264, VC-1, MPEG-2, ... • Scalable Architecture Enables software programmable HDTV video codec • Small Core Size / Low Power For high volume markets

  30. ON DEMANDMicroelectronics Design Center ViennaTechgate,Donau-City-Str.1A-1220 Vienna / Austria www.ondemand.co.at gkrottendorfer@ondemand.co.at

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