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4. Fault Modeling

4. Fault Modeling. Fault Modeling. Why fault modeling? Stuck-at 0/1 fault model The single fault assumption Bridging and delay faults MOS transistors and CMOS Switch-level fault model – Stuck-on/open. Fault Modeling. Fault Model:

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4. Fault Modeling

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  1. 4. Fault Modeling

  2. Fault Modeling • Why fault modeling? • Stuck-at 0/1 fault model • The single fault assumption • Bridging and delay faults • MOS transistors and CMOS • Switch-level fault model • – Stuck-on/open

  3. Fault Modeling • Fault Model: • a set of assumed faults in a system such that testing for them will test for most faults of a specific class. • Used for: • Designing error detection mechanisms • Designing test procedure • Fault simulation • Quality evaluation • Hide complexities of actual defects. Infinitely many defects possible. • Based on past knowledge of defect modes and modeling experience.

  4. Common Fault Models • No model: test exhaustively • Hardware fault models: • – Gate level: • stuck-at 0/1 • bridging • delay faults • – Transistor level: • stuck on/open • bridging • – Functional fault models • Software fault model • – Is there one?

  5. Failure mechanisms in hardware • Temporary • Permanent • – Opens: broken connection, also near-opens • – Shorts: unwanted connection, also near shorts • – Can be seen • Imperfect devices

  6. Stuck-at 0/1 Model • Model: any one or more of these may be stuck at 0 or 1: a gate input, a gate output

  7. Stuck-at 0/1 Example

  8. Bridging (Short) Fault Model • Common assumption: only nearby lines can be bridged • Model: Two lines x and y bridged can cause both to take the value • – x AND y AND-bridging (0-dominance) • – x OR y OR-bridging (1-dominance) • – Depends on technology, transistor dimensions etc.

  9. Bridging Fault Example

  10. Delay Fault Model

  11. MOS Transistors

  12. CMOS NOR Gate

  13. Switch-level Fault Model (1)

  14. Switch-level Fault Model (2): Stuck-ON

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