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Presented by: Joydip Das ~~~ Oct. 21, 2005

Presentation on: Adiabatic Circuits. Presented by: Joydip Das ~~~ Oct. 21, 2005. Adiabatic Circuits. Contents: History of Adiabatic Computing Basics of Adiabatic Computing Proposed Adiabatic Circuits Proposed Clock Generation Circuits Integration with Standard CMOS Systems

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Presented by: Joydip Das ~~~ Oct. 21, 2005

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  1. Presentation on: Adiabatic Circuits Presented by: Joydip Das ~~~ Oct. 21, 2005

  2. Adiabatic Circuits • Contents: • History of Adiabatic Computing • Basics of Adiabatic Computing • Proposed Adiabatic Circuits • Proposed Clock Generation Circuits • Integration with Standard CMOS Systems • My Plans Presented by: Joydip Das on Oct. 21, 2005

  3. Adiabatic Circuits • History of Adiabatic Computing: • The first paper: Boyd G. Watkins, “A low-power multiphase circuit technique,” IEEE Journal of Solid-State Circuits, pp. 213-220, Dec. 1967 • ’60s – ’80s: Researches in IBM (Bennett & Landauer), MIT, Caltech on computational and reversible computation • 1992: Introduction of the term: Adiabatic Circuits by: J. G. Koller and W. C. Athas, “Adiabatic switching, low energy computing, and the physics of storing and erasing information,” PhysComp ’92: Proc. of the Workshop on Physics and Computation, Oct 2-4, 1992, Dallas Texas • 2002: Formation of Adiabatic Logic Ltd., a company to deliver adiabatic products & services. Developed an output driver for ICs that can save up to 75% power in inter-chip communications Presented by: Joydip Das - Oct. 21, 2005

  4. Adiabatic Circuits • History - Researches: • Mid- & Late ’90s:Koller & Athas (USC), Roy (Purdue), Oklobdzija (Berkeley), Dickinson & Denker (Berkeley), Vivek De (Georgia Tech), Younis & Knight (MIT), Moon & Jeong (National Uni., Seoul), Kim & Papaefthymiou (Ann Arbor) etc. • Recent: Kim & Papaefthymiou (Ann Arbor), Roy (Purdue), Michael Frank (FSU), Amirante (Tech. Uni. of Munich), Wang, Liu, Xiao & Huang (Ningbo Uni., China), Salama (UoT) • Areas of Research: Physics of Computing, Prospective Applications,Circuit Design, System Design, Clock-supply generation Presented by: Joydip Das - Oct. 21, 2005

  5. Adiabatic Circuits • Is it Worthy despite: • The constraints:Complex design procedure, extra overhead, slow operation, requirements for new manufacturing procedures • Yes, because: • In some cases (e.g., in sensor network, applications of handheld devices etc.), we are more concerned about energy rather than speed. • Also, it is becoming increasingly difficult to control the heat, generated due to the irreversible computing by ever-increasing no. of gates and switching of conventional circuits. • This technique can reduce power without scaling down voltage and thus may help addressing the leakage power issue etc... Presented by: Joydip Das - Oct. 21, 2005

  6. Q=CV, E=CV2 Vin = 0 Q=CV, E=½CV2 Adiabatic Circuits • Basics of Adiabatic Circuits: • Conventional CMOS: When PFET is Switched ON, Energy from Source=CV2 Energy in Capacitor= ½CV2 Energy Lost = ½CV2 -> PFET When NFET is Switched, Energy Drained= ½CV2 Energy Lost = ½CV2 -> NFET A switching event always dissipates energy equal to signal energy, ½CV2 Presented by: Joydip Das - Oct. 21, 2005

  7. Adiabatic Circuits • Basics of Adiabatic Circuits: Adiabatic Charging: (Koller & Athas, 1992) Q = CV I = Q/T = CV / T Ed = I2RT = (CV/T)2RT = (2RC/T) (½CV2) = (2RC/T) * Signal Energy Compare with thermodynamic adiabatic principle: Very slow changes dissipate less energy. For infinitely slow changes, total dissipation will be zero, resulting in Brownian Computers Presented by: Joydip Das - Oct. 21, 2005

  8. Adiabatic Circuits • Basics of Adiabatic Circuits: Adiabatic Switching: Koller & Athas, 1992 • Three-valued logic used – True, False, de-Energized • When the output is de-Energized, the inputs can be changed with dissipation of energy • The inputs are changed to a stable value • Output states are changed by ramping up the supply voltage • Outputs are changed and get stable • Once stable, outputs can be used for the next stage Presented by: Joydip Das - Oct. 21, 2005

  9. Adiabatic Circuits • Basics of Adiabatic Circuits: Adiabatic Switching - Example: Koller & Athas, 1992 • X, Ys get stable • S2 and S1 are closed • Charge flows to Z or Z‘ • When Z or Z’ is fully charged, S2 is opened • Z or Z’ now maintains • states and can be used in following stages • To discharge, S2 is closed again • RC/T is controlled by controlling T through L Presented by: Joydip Das - Oct. 21, 2005

  10. Adiabatic Circuits • Basics of Adiabatic Circuits: Adiabatic Latch and Inevitable Energy Loss: Koller & Athas, 1992 • Z, Z‘ are charged; S, S are opened. Z, Z’ maintain states through PFETs • During de-Energizing, charge flows from output to supply adiabatically and dissipates energy 1/Tuntil output gets down to Vth. The remaining energy ½CVth2 is lost as heat • ½ CVth2is the irreducible energy lossand can not be recovered • We can not break kT barrier (kT can not be bigger than switch sensitivity, ½CgVth2, due to thermal noise)

  11. Adiabatic Circuits • Basics of Adiabatic Circuits: Characteristics of Adiabatic CMOS Circuits: Koller & Athas, 92 • The energy dissipation of combinational logic can be made arbitrarily small • Information loading into memory circuits consume small amount of energy • Erasing last copy of a piece of information inevitably dissipates an irreduciblefinite amount of energy Presented by: Joydip Das - Oct. 21, 2005

  12. Adiabatic Circuits • Basics of Adiabatic Circuits: Power Supply of Adiabatic CMOS Circuits: • Inputs of one stage needs to be stable before they are applied • While inputs are asserted, the supply is in evaluation mode • Outputs of one stage needs to be stable while evaluated by the next stage • Energy is recovered during the ramp-down of the power supply. • While output is de-energized, the power supply is idle Presented by: Joydip Das - Oct. 21, 2005

  13. Evaluate Hold Discharge Idle Adiabatic Circuits • Basics of Adiabatic Circuits: Power Supply of Adiabatic CMOS Circuits: Presented by: Joydip Das - Oct. 21, 2005

  14. Adiabatic Circuits • Some of the Proposed Adiabatic Circuits: Based on Power Supply & Consequent Evaluation: • 2N-2N2D, 2N-2P, ECRL (Efficient Charge Rec. Logic), PAL (Pass-Transistor Adia. Logic), TSEL (True Single Phase Adia. Logic), QSERL (Quasi-Static Energy Recovery Logic) etc. • All the earlier designs applied multi-phase trapezoidal power supplies. Some of them use six- or more phases. Some used diodes to maintain reversibility • Some of the recent proposals use sinusoidal waves’ characteristics instead of multi-phase trapezoidal waves Presented by: Joydip Das - Oct. 21, 2005

  15. Adiabatic Circuits • Some of the Proposed Adiabatic Circuits: Inverters – ECRL (Moon & Jeong, 1996): Circuit – No Diode Outputs Energy is oscillating and increases with time Chains Presented by: Joydip Das - Oct. 21, 2005

  16. Adiabatic Circuits • Some of the Proposed Adiabatic Circuits: Inverters – ECRL (Moon & Jeong, 1996): Energy Comparison Presented by: Joydip Das - Oct. 21, 2005

  17. Adiabatic Circuits • Some of the Proposed Adiabatic Circuits: Positive Feedback Adiabatic Logic (Amirante et. al., 2003): General Schematic: Cross-coupled transistors form the adiabatic block Only NMOS used for combinational blocks F and F' blocks are realized by static design Presented by: Joydip Das - Oct. 21, 2005

  18. Adiabatic Circuits • Some of the Proposed Adiabatic Circuits: Positive Feedback Adiabatic Logic (Amirante et. al., 2003): 1-Bit Full-Adder: Circuit Energy Diagram Presented by: Joydip Das - Oct. 21, 2005

  19. Adiabatic Circuits Some of the Proposed Adiabatic Circuits: QSERL (Yiben Ye & Roy, 1997, 2001, (?)2005): • Sinusoidal supply used • Easily convertible from static • Eval. – Four Cases possible: • X-Low & pMOS-ON: X follows supply phi to HIGH • X-Low & nMOS-ON: X remains low->no transition • X-High & pMOS-ON: X remains high->no transition • X-High & nMOS-ON: X follows phi to LOW Presented by: Joydip Das - Oct. 21, 2005

  20. Adiabatic Circuits Some of the Proposed Adiabatic Circuits: QSERL 8 X 8 Multiplier: • Organization was identical with CMOS carry-save multiplier • Multiplier was simulated using MOSIS 0.5 μm CMOS n-well process • Compared with static CMOS with same transistor sizing Observations: High clock frequency reduces energy savings. The diode sizing increases and consequently RC/T dissipation increases Throughput is reasonable. Latency is large – twelve clock phases Presented by: Joydip Das - Oct. 21, 2005

  21. Adiabatic Circuits Some of the Proposed Adiabatic Circuits: TSEL (Kim & Papaefthymiou, 2001, 2005): Presented by: Joydip Das - Oct. 21, 2005

  22. Adiabatic Circuits Clock Generation Circuits: Clockwise: QSERL, Four-Phase, True-Single Phase Observations: LC tank oscillator is used to generate power supplies (clock) for adiabatic circuits Presented by: Joydip Das - Oct. 21, 2005

  23. Adiabatic Circuits My Works: • Testing the existing techniques in 0.13μm technology • Effect due to low voltage swing available (0.3-1.2) • Ramping up between these voltage swings • Capacitances that become prominent • Estimation of the leakage power of the existing techniques - WIP • Design of clock generation circuits • Design of adder circuit using adiabatic technique Presented by: Joydip Das - Oct. 21, 2005

  24. Adiabatic Circuits My Works – Simulation: ECRL – Circuit: Presented by: Joydip Das - Oct. 21, 2005

  25. Adiabatic Circuits My Works – Simulation: ECRL – Clock & Power: Presented by: Joydip Das - Oct. 21, 2005

  26. Adiabatic Circuits My Works – Simulation: PFAL – Circuit (Amirante et. al., 03): Presented by: Joydip Das - Oct. 21, 2005

  27. Adiabatic Circuits My Works: PFAL – Waves: Presented by: Joydip Das - Oct. 21, 2005

  28. Adiabatic Circuits My Works: PFAL – Power: Presented by: Joydip Das - Oct. 21, 2005

  29. Questions ? Thank You

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