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Outline

R/O concept of the MVD demonstrator C.Schrader , S. Amar-Youcef, A. Büdenbender, M. Deveaux, D. Doering, J. Heuser, I. Fröhlich, J. Michel, C. Müntz, S. Seddiki, J. Stroth, T. Tischler, and B. Wiedemann. Outline. readout concept of the MVD demonstrator hardware components data processing

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  1. R/O concept of the MVD demonstratorC.Schrader, S. Amar-Youcef, A. Büdenbender, M. Deveaux, D. Doering, J. Heuser, I. Fröhlich, J. Michel, C. Müntz, S. Seddiki, J. Stroth, T. Tischler, and B. Wiedemann

  2. Outline readout concept of the MVD demonstrator • hardware components • data processing • first results of measurements subjects of this talk

  3. Overview of hardware components 2x mimosa20 Demo-Aux-PCB MAPS add-on board analogue output sync. signals or data transfer: OP-link data transfer: I/O-card flex-print-cable Trb2 support monitoring PC storage data transfer: in future: optical link (trb2) at present: I/O-card

  4. Functionality of demo-Aux board MAPS add-on-board demo- Aux board: • analogue buffers for pixel data transfer • low voltage regulated power supply for Mi20-chips • chip slow control wire JTAG • convert of the analogue temperature signals to analog LVDS signals • convert of the LVTTL sync. signals from M20-chip to digital LVDS signals Mi20 Mi20 Demo-Aux-board 50 PIN SUB-D Con Flex-Con Flex-cable will be developed by IKF < 5cm • mimosa20: • 4x analogue differential signal outputs • for long-distance data transfer • LVTTL sync. signals for chip controlling • 4x analogue signals for temperature monitoring status of the demo-Aux: advanced schematics

  5. Functionality of the add-on board mimosa20 demonstrator: 2x mimosa, parallel readout, 360 x 640 pixel/frame, 50MHz  2.4Gbit/s, uncompressed • platform to study online data specification for data reduction • close to hardware for chip integration in future times • compatibility with HADES DAQ (Trb2) for testing purposes CBM:~2Gbit/s compressed see talk of S. Seddiki This data rate is too high for data storage systems online data reduction developed by IKF add-on board with a FPGA as reconfigurable hardware status: 12 layer board is completed and tested

  6. Components of the add-on-board 4x diff. analogue pixel data signals LVDS digital sync. signals • differential-to-differential amplifier to • balance the analogue input for the ADCs • 4 x 12bit ADCs to read out the analogue output signal of the two chips • LVDS differential drivers and receivers • for chip controlling • Virtex IV LX 40 FPGA and memory banks • for online data-processing • two high-speed connectors (15Gbit/s) • for data transfer towards the Trb2-board I/O from demo-Aux add-on-board

  7. Trb2 and Add-on board concept • the Trb2 (HADES) has been designed in a way to be detector independent by using a flexible add-on board concept • the MAPS Add-on board is mounted on the Trb2 back side • Trb2 provides: • high data-rate digital interface • connector (15Gbit/s) • FPGA configuration • high data transfer with optical link (2Gbit/s), in future • application process interface (API) • power supply +5V,10A • clock distribution the general-propose trigger and readout board (Trb2) status: the Trb2-Add-on concept is in use

  8. Data processing pipelined algorithms for real-time application in stream mode processing steps: • correlated double sampling (CDS) • bit reduction • threshold (for hit identification) • cluster finding (the hit and the 8 neighbor pixels are important) zero suppression

  9. ADC calibration devices intrinsic uncertainly: Integral Nonlinearity error (INL) = ±1.6LSB± 2LSB ADC OP... result: the difference of ideal and actual value is: ±2 ADC counts uncertainties are dominated by ADC readout chain is OK with error bars without error bars calibration terms are included in data processing

  10. First measurement results (mimosa20) digital sync. signals for chip controlling analogue raw pixel data converted by 12bit ADC marker pixel 32 µs measured sub matrix with pixel defects

  11. Project status Hardware: • add-on board: design  manufacturing  test  • I/O interface to PC side: installation  firmware development  test  • demo-Aux board: specification  ongoing design, manufacturing Nov2008 Data processing: • VHDL: CDS  bit-reduction  threshold  data-output-interface cluster finding (S. Seddiki)‏: specification  ongoingimplementation • data acquisitionand storage software for PC : development  installation test 

  12. THANK YOU

  13. Correlated double sampling by Self-Bias-Pixel Fig.8: The behaviour of SB-pixels is observed by frames. The constant current leakage in the capacitor is compensate through a diode. After hit the diode re-fill the capacitor ADC units 1900 fx:px threshold hit fx-1:px readout cycle ∆ ADC (fx:px - fx-1:px)‏ Fig.9: Equivalent circuit diagram of SB-Pixel threshold Fig.10: AfterCDS clear hit identification is possible (fx-1:px - fx-2:px)‏ acquisition cycle

  14. Threshold The hit and the 8 neighbour pixels are important Result: not the complete matrix is readout, only the hit with the neighbour pixel Fig.12: Data selection with threshold

  15. Add-on board design Fig.11: Add-on board

  16. bit-flipping % constant power supply:~503mV± 10µV RESULT: last bit is flipping % % % % % % Digital code [ADC counts]

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