Theory of Compilation 236360 Erez Petrank

1. Lecture 10: Code Generation Theory of Compilation 236360Erez Petrank

2. Source text txt Executable code exe You are here Compiler LexicalAnalysis Syntax Analysis SemanticAnalysis Inter.Rep.(IR) Code Gen. characters tokens AST (Abstract Syntax Tree) Annotated AST

3. Code Generation: Backend • Generate code for a specific machine. • Assume no errors at this point. • Input: Intermediate language code + symbol table • Output: target language code

4. target languages Absolute machine code Code Gen. IR + Symbol Table Relativemachine code Assembly

5. From IR to ASM: Challenges • mapping IR to ASM operations • what instruction(s) should be used to implement an IR operation? • how do we translate code sequences • call/return of routines • managing activation records • memory allocation • register allocation • optimizations

6. Intel IA-32 Assembly • Going from Assembly to Binary… • Assembling • Linking • AT&T syntax vs. Intel syntax • We will use AT&T syntax • matches GNU assembler (GAS)

7. AT&T versus Intel Syntax

8. IA-32 Registers • Eight 32-bit general-purpose registers • EAX – accumulator for operands and result data. Used to return value from function calls. • EBX – pointer to data. Often use as array-base address • ECX – counter for string and loop operations • EDX – data/general • ESI – GP and source pointer for string operations • EDI – GP and destination pointer for string operations • EBP – stack frame (base) pointer • ESP – stack pointer • EFLAGS register • EIP (instruction pointer) register • … (ignore the rest for our purposes)

9. Not all registers are born equal • EAX • Required operand of MUL,IMUL,DIV and IDIV instructions • Contains the result of these operations • EDX • Stores remainder of a DIV or IDIV instruction (EAX stores quotient) • ESI, EDI • ESI – required source pointer for string instructions • EDI – required destination pointer for string instructions • Destination Registers of Arithmetic operations • EAX, EBX, ECX, EDX • EBP – stack frame (base) pointer • ESP – stack pointer

10. IA-32 Addressing Modes • Machine-instructions take zero or more operands • Source operand • Immediate • Register • Memory location • (I/O port) • Destination operand • Register • Memory location • (I/O port)

11. Immediate and Register Operands • Immediate • Value specified in the instruction itself • GAS syntax – immediate values preceded by $ • add $4, %esp • Register • Register name is used • GAS syntax – register names preceded with % • mov%esp,%ebp

12. Memory and Base Displacement Operands • Memory operands • Value at given address • GAS syntax - parentheses • mov (%eax), %eax • Base displacement • Value at computed address • Address computed out of • base register, index register, scale factor, displacement • offset = base + (index*scale) + displacement • Syntax: disp(base,index,scale) • movl   $42, $2(%eax) • movl $42, $1(%eax,%ecx,4)

13. Base Displacement Addressing 4 4 4 4 4 4 4 4 7 0 2 4 5 6 7 1 (%ebx,%ecx,4) Array Base Reference Mov (%ebx,%ecx,4), %eax %ebx= base %ecx= 3 Addr = base + (index*scale) + displacement Addr = base + (3*4) + 0 = base + 12

14. Basic Blocks • An important notion. • Start by breaking the IR into basic blocks • A basic block is a sequence of instructions with • A single entry (to first instruction), no jumps to the middle of the block • A single exit (last instruction) • Thus, code execute as a sequence from first instruction to last instruction without any jumps • An edge from one basic block B1 to another block B2 when the last statement of B1 may jump to B2

15. Example B1 t1 := 4 * i t2 := a [ t1 ] if t2 <= 20 gotoB3 False True t3 := 4 * i t4 := b [ t3 ] gotoB4 B2 B3 t5 := t2* t4 t6:= prod + t5 prod := t6 gotoB4 B4 t7:= i + 1 i := t2 Goto B5

16. creating basic blocks • Input: A sequence of three-address statements • Output: A list of basic blocks with each three-address statement in exactly one block • Method • Determine the set of leaders(first statement of a block) • The first statement is a leader • Any statement that is the target of a conditional or unconditional jump is a leader • Any statement that immediately follows a goto or conditional jump statement is a leader • For each leader, its basic block consists of the leader and all statements up to but not including the next leader or the end of the program

17. B1 control flow graph prod := 0 i := 1 • A directed graph G=(V,E) • nodes V = basic blocks • edges E = control flow • (B1,B2) E if control from B1 flows to B2 • A loop is a strongly connected component of the graph that has a single entry point. • An inner loop is a loop that has no sub-loop. B2 t1 := 4 * i t2 := a [ t1 ] t3 := 4 * i t4 := b [ t3 ] t5 := t2* t4 t6:= prod + t5 prod := t6 t7:= i + 1 i := t7 if i <= 20 gotoB2

18. CFG IR example for i from 1 to 10 do for j from 1 to 10 do a[i, j] = 0.0; for i from 1 to 10 do a[i, i] = 1.0; source B1 i = 1 B2 j = 1 • i = 1 • j =1 • t1 = 10*I • t2 = t1 + j • t3 = 8*t2 • t4 = t3-88 • a[t4] = 0.0 • j = j + 1 • if j <= 10 goto (3) • i=i+1 • if i <= 10 goto (2) • i=1 • t5=i-1 • t6=88*t5 • a[t6]=1.0 • i=i+1 • if I <=10 goto(13) t1 = 10*I t2 = t1 + j t3 = 8*t2 t4 = t3-88 a[t4] = 0.0 j = j + 1 if j <= 10 gotoB3 B3 B4 i=i+1 if i <= 10 gotoB2 B5 i = 1 B6 t5=i-1 t6=88*t5 a[t6]=1.0 i=i+1 if I <=10 gotoB6

19. Optimizations • Possible to obtain performance improvements by working inside basic block boundaries. • A better accuracy is obtained when considering all blocks in a routine. • It is best to consider all blocks in the program (whole program analysis). But: • Costly • Usually unknown. • Optimization employs “program understanding” = program analysis. • An example: to allocate registers efficiently we need to analyze liveness of variables.

20. Variable Liveness • A statement x = y + z • defines x • uses y and z • A variable x is live at a program point if its value is used at a later point without being defined beforehand • If x is defined in instruction i, used in instr. j, and there is a computation path from i to j that does not modify x, then instr. j is using the value of x that is defined in instr. i. y = 42 z = 73 x = y + z print(x); x undef, y live, z undef x undef, y live, z live x is live, y dead, z dead x is dead, y dead, z dead (showing state after the statement)

21. Computing Liveness Information • between basic blocks – dataflow analysis (next lecture) • within a single basic block? • idea • use symbol table to record next-use information • scan basic block backwards • update next-use for each variable

22. Computing Liveness Information • INPUT: A basic block B of three-address statements. symbol table initially shows all non-temporary variables in B as being live on exit. • OUTPUT: At each statement i: x = y + z in B, liveness and next-use information of x, y, and z at i. • Algorithm:Start at the last statement in B and scan backwards • At each statement i: x = y + z in B, we do the following: • Attach to i the information currently found in the symbol table regarding the next use and liveness of x, y, and z. • In the symbol table, set x to "not live" and "no next use.“ • In the symbol table, set y and z to "live" and the next uses of y and z to i

23. Computing Liveness Information • Start at the last statement in B and scan backwards • At each statement i: x = y + z in B, we do the following: • Attach to i the information currently found in the symbol table regarding the next use and liveness of x, y, and z. • In the symbol table, set x to "not live" and "no next use.“ • In the symbol table, set y and z to "live" and the next uses of y and z to i x = 1 y = x + 3 z = x * 3 x = x * z can we change the order between 2 and 3?

24. common-subexpression elimination • common-subexpression elimination • Easily identified by DAG representation. a = b + c b = a - d c = b + c d = a - d a = b + c b = a - d c = b + c d = b

25. DAG Representation of Basic Blocks a = b + c b = a - d c = b + c d = a - d c + - b,d d + a b c

26. Use indices to distinguish variable assignments a = b + c b = a - d c = b + c d = a - d c + - b,d d0 + a b0 c0

27. DAG and Dead Code a = b + c b = b - d c = c + d e = b + c + e + - + b c a b0 c0 d0 • Perform dead code elimination. • Assume a is not used outside the block.

28. algebraic identities a = x^2 b = x*2 e = x*2i c = x/2i d = 1*x f = x+0 a = x*x b = x+x e = shift(x,i) c = shift(x,-i) d = x f = x

29. simple code generation • registers • used as operands of instructions • can be used to store temporary results • can (should) be used as loop indexes due to frequent arithmetic operation • used to manage administrative info (e.g., runtime stack) • Number of registers is limited • Need to allocate them in a clever way • Critical for program efficiency.

30. simple code generation • assume machine instructions of the form • LD reg, mem • ST mem, reg • OP reg,reg,reg • further assume that we have all registers available for our use • ignore registers allocated for stack management

31. simple code generation • Translate each 3AC instruction separately • A register descriptor keeps track of the variable names whose current value is in that register. • we use only those registers that are available for local use within a basic block, we assume that initially, all register descriptors are empty. • As code generation progresses, each register will hold the value of zero or more names. • For each program variable, an address descriptor keeps track of the location or locations where the current value of that variable can be found. • The location may be a register, a memory address, a stack location, or some set of more than one of these • Information can be stored in the symbol-table entry for that variable

32. simple code generation For each three-address statement x := y op z, • Invoke getreg(x := y op z) to select registers Rx, Ry, and Rz. • If Ry does not contain y, issue: “LD Ry, y’ ”, for a location y’ of y. • If Rz does not contain z, issue: “LD Rz, z’ ”, for a location z’ of z. • Issue the instruction “OP Rx,Ry,Rz” • Update the address descriptors of x, y, z, if necessary. • Rxis the only location of x now, and Rx contains only x (remove Rx from other address descriptors).

33. updating descriptors • 1. For the instruction LD R, x • Change the register descriptor for register R so it holds only x. • Change the address descriptor for x by adding register R as an additional location. • 2. For the instruction ST x, R • change the address descriptor for x to include its own memory location.

34. updating descriptors • 3.For an operation such as ADD Rx, Ry, Rz, implementing a 3AC instruction x = y + z • Change the register descriptor for Rx so that it holds only x. • Change the address descriptor for x so that its only location is Rx. Note that the memory location for x is not now in the address descriptor for x. • Remove Rx from the address descriptor of any variable other than x. • 4. When we process a copy statement x = y, after generating the load for y into register Ry, if needed, and after managing descriptors as for all load statements (rule 1): • Add x to the register descriptor for Ry. • Change the address descriptor for x so that its only location is Ry.

35. example R2 R3 B C t u v R1 A D t= A – B u = A- C v = t + u A = D D = v + u A B C D t = A – B LD R1,A LD R2,B SUB R2,R1,R2 R2 R3 B C t u v R1 A D A t A,R1 B C D R2 u = A – C LD R3,C SUB R1,R1,R3 R2 R3 B C t u v R1 A D u t C A B C,R3 D R2 R1 v = t + u ADD R3,R2,R1 R2 R3 B C t u v R1 A D u t v A B C D R2 R1 R3 A B C D = live outside the block t,u,v = temporaries in local storate

36. example R2 R3 B C t u v R1 A D t= A – B u = A- C v = t + u A = D D = v + u u t v A B C D R2 R1 R3 A = D LD R2, D R2 R3 B C t u v R1 A D u A,D v R2 B C D,R2 R1 R3 D = v + u ADD R1,R3,R1 R2 R3 B C t u v R1 A D D A v R2 B C R1 R3 exit ST A, R2 ST D, R1 R2 R3 B C t u v R1 A D D A v A,R2 B C D,R1 R3 A B C D = live outside the block t,u,v = temporaries in local storate

37. design of getReg • many design choices • simple rules • If y is currently in a register, pick a register already containing y as Ry. No need to load this register • If y is not in a register, but there is a register that is currently empty, pick one such register as Ry • complicated case • y is not in a register, but there is no free register

38. design of getReg • instruction: x = y + z • y is not in a register, no free register • let R be a taken register holding value of a variable v • possibilities: • if v is x, the value computed by the instruction, we can use it as Ry (it is going to be overwritten anyway) • if v is not used later (dead), we can use R as Ry • if the value v is available somewhere other than R, we can allocate R to be Ry (just by updating descriptors). • otherwise: spill the value to memory by ST v,R

39. global register allocation • so far we assumed that register values are written back to memory at the end of every basic block • want to save load/stores by keeping frequently accessed values in registers • e.g., loop counters • idea: compute “weight” for each variable • for each use of v in B prior to any definition of v add 1 point • for each occurrence of v in a following block using v add 2 points, as we save the store/load between blocks • cost(v) = Buse(v,B) + 2*live(v,B) • use(v,B) is the number of times v is used in B prior to any definition of v • live(v, B) is 1 if v is live on exit from B and is assigned a value in B • after computing weights, allocate registers to the “heaviest” values

40. Example bcdf a = b + c d = d - b e = a + f B1 acdef acde acdf B3 f = a - d b = d + f e = a – c B2 cdef bcdef b,d,e,f live cdef b = d + c B4 cost(a) = Buse(a,B) + 2*live(a,B) = 4 cost(b) = 6 cost(c) = 3 cost(d) = 6 cost(e) = 4 cost(f) = 4 bcdef b,c,d,e,flive

41. Example LD R1,b LD R2,d LD R3,c ADD R0,R1,R3 SUB R2,R2,R1 LD R3,f ADD R3,R0,R3 ST e, R3 B1 LD R3,f ADD R1,R2,R3 LD R3,c SUB R3,R0,R3 ST e, R3 SUB R3,R0,R2 ST f,R3 B2 B3 ST b,R1 ST a,R2 LD R3,c ADD R1,R2,R3 B4 ST b,R1 ST d,R2

42. Register Allocation by Graph Coloring • Address register allocation by • Spilling operations are costly – minimize them. • Finding register allocation that minimizes spilling is NP-Hard. • We use heuristics from graph coloring. • Main idea • register allocation = coloring of an interference graph • every node is a variable • edge between variables that “interfere” = are both live at the same time • number of colors = number of registers

43. Example V2 V3 • Analyze liveness • Build interference graph • If interfering vertices get the same register (color), then a spill is needed. V1 V4 V8 V7 V5 V6 time v1 v5 v8 v2 v7 v3 v4 v6

44. But note that interference is conservative a = read(); b = read(); c = read(); a = a + b + c; if (a<10) { d = c + 8; print(c); } else if (a<2o) { e = 10; d = e + a; print(e); } else { f = 12; d = f + a; print(f); } print(d); B1 a = read(); b = read(); c = read(); a = a + b + c; if (a<10) goto B2 else goto B3 b a c B2 B3 d = c + 8; print(c); d if (a<20) goto B4 else goto B5 B4 e B5 e = 10; d = e + a; print(e); f d f = 12; d = f + a;print(f); d B6 print(d);

45. Example: Interference Graph a = read(); b = read(); c = read(); a = a + b + c; if (a<10) goto B2 else goto B3 b a c f a b B2 B3 d d = c + 8; print(c); if (a<20) goto B4 else goto B5 d e c B4 e f B5 e = 10; d = e + a; print(e); d d f = 12; d = f + a;print(f); B6 print(d);

46. Register Allocation by Graph Coloring • variables that interfere with each other cannot be allocated the same register • graph coloring • classic problem: how to color the nodes of a graph with the lowest possible number of colors • bad news: problem is NP-complete (to even approximate) • good news: there are pretty good heuristic approaches

47. Heuristic Graph Coloring • idea: color nodes one by one, coloring the “easiest” node last • “easiest nodes” are ones that have lowest degree • fewer conflicts • algorithm at high-level • find the least connected node • remove least connected node from the graph • color the reduced graph recursively • re-attach the least connected node

48. Heuristic Graph Coloring f a b f a d e c d e c stack:  stack: b f a f d e d e stack: acb stack: cb

49. Heuristic Graph Coloring f f f d e d stack: acb stack: eacb stack: deacb stack: fdeacb f1 f1 f1 f1 a2 d2 d2 e1 d2 e1 stack: eacb stack: deacb stack: acb stack: cb

50. Heuristic Graph Coloring f1 a2 f1 a2 c1 d2 e1 d2 e1 stack: cb stack: b Result: 3 registers for 6 variables Can we do with 2 registers? b3 f1 a2 c1 d2 e1 stack: 