Automatic Synthesis and Code-Generation of Real-Time Embedded Software 即時嵌入式軟體之自動合成及程式碼之產生

1. Automatic Synthesis and Code-Generation of Real-Time Embedded Software 即時嵌入式軟體之自動合成及程式碼之產生 熊博安 國立中正大學資訊工程學系 民國九十一年四月二十六日

2. What will I talk about ? • What is a real-time system? • What is an embedded system? • Why software? • Why synthesis? • What is software synthesis & code generation? • Real-world applications? • Future work?

3. What is a REAL-TIME SYSTEM? • Timely Response • Predictable Response • System Correctness: • Timing (period, deadlines, etc.) • Function • Constraints: • Hard (meet ALL deadlines) • Soft (miss SOME deadlines)

4. Examples of Real-Time Systems air crafts telecommunications automobiles multimedia servers

5. What is an EMBEDDED SYSTEM? • Installed in a larger system • Dedicated task • Small Memory Space (200~400 KB) • Low Processing Power (100~200 MHz) • Unstable Environment (mobile, …) • Reactive • Real-Time

6. Embedded Systems Example research lab equipments space crafts factory automation home appliances office equipments medical instruments

7. Embedded System Architecture

8. Why SOFTWARE? • more than 70% software in many real-time embedded systems!!! • software is more flexible and easily reconfigurable, hence more errors!!! • real-time  need for temporally correct software • embedded  need for small, efficient software

9. Why SYNTHESIS? • More software  high complexity  need for automatic design (synthesis) • Eliminate human and logical errors • Relatively immature synthesis techniques for software • Code optimizations • size • efficiency • Automatic code generation

13. What is software synthesis & code generation? • Model for real-time embedded systems?Set of concurrent tasks with memory and timing constraints! • How to feasibly execute in an embedded system? (e.g. a 100MHz CPU, 256 KB RAM)Task scheduling! • How to generate code?Map schedules to software code! • Code optimizations?Minimize size, maximize efficiency!

14. Bounded Memory Execution • Real-Time Constraints Hard Real-Time Soft Real-Time Extended Quasi-Static Scheduling (EQSS) Real-Time Scheduling (RTS) Firing Interval Bound Synthesis (FIBS) Synthesis Issues and Solutions Proposed Solutions:

15. Real-Time Embedded System Model Time Complex-Choice Petri Nets (TCCPN)

16. Synthesis Algorithm (Hard RTES) Synthesize_Hard_RTES(S, ,  ) { • EQSS = Ext_Quasi_Static_Schedule(S, ); • if (EQSS == NULL) return MemOverFlow; • RTS = Real_Time_Sched(S, QSS,  ); • if (RTS == NULL) return RTS_Error; else Code = Code_Gen(S, QSS, RTS); • return Code; }

17. Synthesis Algorithm (Soft RTES) Synthesize_Soft_RTES(S, ,  ) { • EQSS = Ext_Quasi_Static_Schedule(S, ); • if (EQSS == NULL) return MemOverFlow; • FIB = Firing_Interv_Synth(S, QSS, ); • if (FIB == NULL) return FIB_Error; else Code = Code_Gen(S, QSS, FIB); • return Code; }

18. net decomposition • Finite Complete Cycle • Deadlock Free • Satisfy Memory Reqts Quasi-Static Scheduling TFCPN Conflict-Free Components MemoryOK!!! Quasi-Static Schedules

19. p1 t4 t1 t5 p2 t2 t6 p3 t3 t7 Exclusion Set Extended Quasi-Static Scheduling TCCPN Exclusion Table

20. p1 t4 t1 t4 t4 t4 t4 t4 t5 p2 t5 t5 t5 t5 t5 t2 t6 t6 t6 t6 t6 t6 p3 t7 t7 t7 t7 t7 t3 t7 Decomposition of Exclusion Set

21. t4 t4 t4 t4 t4 t4 t4 t5 t5 t5 t5 t5 t5 t5 t6 t6 t6 t6 t6 t6 t6 t7 t7 t7 t7 t7 t7 t7 Reduction of Decomposed Exclusion Set Reduce

22. p1 p1 t4 t1 t1 t5 p2 p2 t2 t2 t6 p3 p3 t3 t7 t3 EQSS Schedules f(s) = (t1 t2 t3 t4 t6) f(s) = (t1 t2 t3 t5 t5 t7)

23. Real-Time Scheduling • Single Processor • Worst Case Timing Analysis: • Rate Monotonic (RM) • fixed priority • small period  high priority • Earliest Deadline First (EDF) • dynamic priority • early deadline  high priority

24. Firing Interval Bound Synthesis • 2 issues in the synthesis of SOFT real-time embedded systems: • Synchronization Wait: (for completion of other tasks) • Real-Time Specification: (complete before deadlines) • Proposed Solutions: • Postpone Release Time:    + w, w> 0 • Advance Finish Time:     n, n>0

25. Code Generation • generate_code(S, QSS1, QSS2, …, QSSn, RTS) { • for i = 1, …, n { • Di = create_process(QSSi); • for j = 1, …, Indep_Tasks(Ai) { • dij = create_task(QSSi); • generate_task_code(dij); • add_task(dij, Di); } • } • create_main(); • output “for(i=0, i<length(RTS); i++) {”; • for k = 1, …, RTS output_code(Dik); • output “}”; • }

26. Processi Task 1 Task 2 Task k … Optimal Code Hierarchy Main Program TCCPN # Tasks = # Independent Source Transitions

27. Illustration Example S = {F1, F2}

28. Conflict Free Components for F1 Quasi-Static Scheduling v11 = (t11, t12, t11, t12, t14) 11  (v11)  22 v12 = (t11, t13, t15, t15) 13  (v12)  26

29. Conflict Free Components for F2 Quasi-Static Scheduling v21 = (t21, t22, 2t24, 4t26, t28,t29, t26)31  (v21)  68 v22 = (t21, t23, t25, 2t27, t28,t29, t26)15  (v22)  36

30. Real-Time Scheduling 1 = {v11, v12} 2 = {v12, t11 t12 k  v12 t11 t12 t14, k  1}

31. ATM Virtual Private Network Server Example WFQ SCHEDULER CLASSIFIER CONGESTION CONTROL (MSD) SUPERVISOR ATM OUT (155 Mbit/s) ATM IN (155 Mbit/s) DISCARDED CELLS

32. ATM Server Example

33. 14 Schedules of MSD in ATM

34. 0 MSD 1 CID 2 PTI 3 t1 4 READ_STATE_VCC 7 READ_OUT_QUID 10 t2 11 t3 t4 t5 12 READ_THRESHOLD 15 CHECK_QLENGTH2 18 t8 19 12 t6 UPDATE_STATE_INIT 13 18 12 READ_MAX_QLENGTH 15 CHECK_QLENGTH1 18 t7 19 t6 UPDATE_STATE_INIT t6 UPDATE_STATE_INIT • 20 • 21 21 • 30 • 31 • 52 20 21 26 30 36 46 37 58 25 26 31 35 41 51 42 63 t11 UPDATE_STATE_REJ • t11 UPDATE_STATE_REJ t10 t9 • 25 • 26 26 • 35 • 36 • 57 PUSH PUSH PUSH t10 t9 UPDATE_STATE_ACC UPDATE_STATE_ACC COMPUTE_OUT_TIME t12 *SCHEDULE_WFQ PUSH COMPUTE_OUT_TIME t12 *SCHEDULE_WFQ COMPUTE_OUT_TIME t12 COMPUTE_OUT_TIME t12 *SCHEDULE_WFQ *SCHEDULE_WFQ *SCHEDULE_WFQ Schedule Results: 49 markings 14 schedules 63 instructions 12 Kbytes Memory

35. Master/Slave Role Switch in the Bluetooth Wireless Comm Protocol • In Bluetooth protocol: • Piconet = 1 master + 7 active slaves • Frequently, master and slave switch roles • new active slave joining piconet • overtaking of master duties • creation of a new piconet with old master as slave • Model • 2 TCCPN for Host A and Host B • 2 TCCPN for Host Control / Link Manager

36. TCCPNs for Host A and Host B

37. TCCPN for Host Control / Link Manager of Device A

38. TCCPN for Host Control / Link Manager of Device B

39. Synthesis Results for M/S switch

40. Mnemonics for Host A Transitions • t_0: Initialize, • t_1: ACL_Connection, • t_2: Send HA2LA_HCI_Switch_Role, • t_3: t4, • t_4: Receive LA2HA_HCI_Command_status_event, • t_5: Receive LA2HA_HCI_Role_change_event, • t_6: End.

41. Mnemonics for HC/LM A Transitions • t_0: Initialize, • t_1: ACL_Connection, • t_2: Receive HA2LA_HCI_Switch_Role, • t_3: Receive N2LA_LMP_Switch_reg, • t_4: Send LA2HA_HCI_Command_States_event, • t_5: Receive N2LA_LMP_Slot_offset_sub1, • t_6: Checking NetWork, • t_7: Send LA2N_LMP_slot_offset_sub2, • t_8: Send LA2N_LMP_not_accepted, • t_9: Send LA2N_LMP_accepted, • t_10: End Checking Network, • t_11: Send LA2N_LMP_Switch_req, • t_12: Receive N2LA_LMP_not_accepted, • t_13: Receive N2LA_LMP_accepted, • t_14: End, • t_15: Send TDD_SwitchA, • t_16: Receive BA2LA_TimeOut1, • t_17: Receive BA2LA_Role_SwitchA_Success, • t_18: End, • t_19: Send LA2HA_HCI_Role_Change_event, • t_20: End

42. Conclusions • Software needs to be synthesized automatically because it is getting more and more complex! • Hard RTES Synthesis Method = EQSS + RTS + Code-Generation • Soft RTES Synthesis Method = EQSS + FIBS + Code-Generation • ATM VPN Server example showsfeasibility of our approach

43. Current and Future Work • Integrate Real-Time Scheduling & EQSS • A general Petri Net system model • Java Implementation: install into embedded systems such as PDA for dynamic code change and management by user (web computing) • C Code Generation: for embedding into prototyping systems such as SoC design and verification platform

44. References (EQSS, FIBS, etc.) • All papers are downloadable at http://www.cs.ccu.edu.tw/~pahsiung/publications/publications.html • F.-S. Su and P.-A. Hsiung, “Extended Quasi-Static Scheduling for Formal Synthesis and Code Generation of Embedded Software,” Proc. of the 10th IEEE/ACM International Symposium on Hardware/Software Codesign, (CODES'02), Colorado, USA, May 6-8, 2002 (accepted for presentation). • P.-A. Hsiung, “Formal Synthesis and Control of Soft Embedded Real-Time Systems,” Proc. 21st IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems (FORTE'01), (Cheju Island, Korea), pp. 35-50, Kluwer Academic Publishers, August 2001. • P.-A. Hsiung, "Formal Synthesis and Code Generation of Embedded Real-Time Software," Proc. ACM/IEEE 9th International Symposium on Hardware/Software Codesign (CODES'01), (Copenhagen, Denmark), pp. 208-213, ACM Press, New York, USA, April 2001.

45. References (Time-Mem Sched.) • P.-A. Hsiung and C.-H. Gau, “Formal Synthesis of Real-Time Embedded Software by Time-Memory Scheduling of Colored Time Petri Nets,” Proc. of the Workshop on Theory and Practice of Timed Systems (TPTS'2002, Grenoble, France), April 6-7, 2002. • C.-H. Gau and P.-A. Hsiung, “Time-Memory Scheduling and Code Generation of Real-Time Embedded Software,” Proc. of the 8th International Conference on Real-Time Computing Systems and Applications (RTCSA'02, Tokyo, Japan), pp. 19-27, March 18-20, 2002.

46. References (VERTAF) • P.-A. Hsiung, T.-Y. Lee, W.-B. See, J.-M. Fu, and S.-J. Chen, "VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems," Proc. of the 5th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC'2002, Washington, D.C., USA), April 29-May 1, 2002 (accepted for presentation). • P.-A. Hsiung, W.-B. See, T.-Y. Lee, J.-M. Fu, and S.-J. Chen, "Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks," Proc. 8th Asia-Pacific Software Engineering Conference (APSEC'01) , (Macau SAR, China), pp. 71-78, IEEE CS Press, December 2001. • P.-A. Hsiung, F.-S. Su, C.-H. Gau, S.-Y. Jeng, and Y.-M. Chang, "Verifiable Embedded Real-Time Application Framework," Proc. IEEE International Real-Time Technology and Applications Symposium (RTAS'01), Work-In-Progress Session, (Taipei, Taiwan), pp. 109-110, IEEE Computer Society Press, May 2001.