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APFEL – MATRIX and the next APFEL Iteration

APFEL – MATRIX and the next APFEL Iteration. Overview . APFEL – MATRIX Setup of 16 crystals Readout system Data acquisition Next APFEL Iteration APFEL design 2010 Outlook. G.Otto, GSI. 1. G.Otto, GSI. G.Otto, GSI. 16. ASIC on a PCB. APD matrix. G.Otto, GSI.

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APFEL – MATRIX and the next APFEL Iteration

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  1. APFEL – MATRIX and the next APFEL Iteration Peter Wieczorek, EE

  2. Overview • APFEL – MATRIX • Setup of 16 crystals • Readout system • Data acquisition • Next APFEL Iteration • APFEL design 2010 • Outlook Peter Wieczorek, EE

  3. G.Otto, GSI 1 G.Otto, GSI G.Otto, GSI 16 ASIC on a PCB APD matrix G.Otto, GSI APFEL - MATRIX • Matrix readout • 16 channels (one APD per crystal) • Separate high voltages • Two channel read out by one ASIC Peter Wieczorek, EE

  4. ASIC APD Crystal DAQ Digitize the analog output signals 101101000011 For the digitization → FEBEX – Board developed at GSI is used Peter Wieczorek, EE

  5. Optical Gbit Interface to DAQ G.Otto, GSI FEBEX - Board Developed by J.Hoffmann LAB: USB - Interface 8 differential analog inputs ADC input range: ± 1 V ADC: 12 Bit, 65 MS/s 2 x 2.5 Gbit/s optical interface Peter Wieczorek, EE

  6. G.Otto, GSI FEBEX 2010 • Existing FEBEX – Board is a first prototype • Pulse shape analysis on the FPGA in development • 8 channels readout version • Internal FPGA memory buffer is large enough for 8 (30) µs traces • Next FEBEX - Board (design 2010) • Upgrade to 16 (32) channels • More powerful FPGA • Pulse shape analysis on the FPGA (will be done at KVI) • Compatible ADCs (10, 12 or 14 Bit; 50 -100 MS/s) • Larger memory (store more than 30 µs time information) • Prototype for a readout of 400 channels Peter Wieczorek, EE

  7. G.Otto, GSI G.Otto, GSI G.Otto, GSI G.Otto, GSI G.Otto, GSI G.Otto, GSI G.Otto, GSI G.Otto, GSI G. Otto,GSI PEXOR – FEBEX Connection FEBEX PEXOR – Board (PCIe) 4x up to 16 FEBEX in series PEXOR – Board was designed by Jan Hoffmann Programming was done by Wolfgang Ott Peter Wieczorek, EE

  8. DAQ Summary To measure 16 differential outputs from the APFEL – Matrix existing DAQ components from GSI are used Digitization and data transport: FEBEX – PEXOR – Board (contact: Jan Hoffmann) DAQ – System:Multi Branch System(MBS) (contact: Wolfgang Ott, Nikolaus Kurz, http://www-win.gsi.de/daq/) Online monitoring / offline analysis: GSI Object Oriented On-line Off-line system (GO4) (contact: Jörn Adamczewski-Musch, http://www-win.gsi.de/go4/) Peter Wieczorek, EE

  9. Go4 MATRIX Display Peter Wieczorek, EE

  10. APFEL - Buffer (GSI) FEBEX - Board (GSI) PEXOR - Board (GSI) APFEL - MATRIX (GSI) HV and Data connectors (GSI) G.Otto, GSI Photo of the APFEL - MATRIX Setup Peter Wieczorek, EE

  11. Next Iteration of the APFEL - ASIC Peter Wieczorek, EE

  12. Layout of the existing ASIC Shaper stage Process: 350 nm – CMOS (AMS) Two equivalent readout channels Programmable voltage references Dimension: 3.3 mm x 3.3 mm Pad connections: 64 Channel 1 Preamplifier stage Output stage Channel 2 Voltage reference Peter Wieczorek, EE

  13. Next Iteration • APFEL03: Manuel voltage reference progamming with lookup tables for different temperatures is necessary → An autocalibration has been developed • To operate the high and low amplification path of a channel in parallel an additional voltage reference DAC has been implemented • For chip identification → Bugfix in chip – ID selection • Open question: Output buffer ??? (final call !!) • Status of the next APFEL – iteration: • Schematic review is done • Layout of the chip is in progress Peter Wieczorek, EE

  14. Outlook • First cosmic tests with the APFEL – MATRIX (Spring 2010) • Submission of the next APFEL – ASIC iteration (Spring 2010) • Commissioning of next APFEL iteration (Summer 2010) • Do we need additional ASICs for further tests (more than 20)? Peter Wieczorek, EE

  15. Peter Wieczorek, EE

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