Meghana Khadkikar Parul Apan Rohini Kulkarni Sidharth Sood Xiaoya Yang

1. First Order IIR Filter using Serial AdderProject for EE166 – spring 2003San Jose State University--------------------------------------------------------------------------- • Meghana Khadkikar • Parul Apan • Rohini Kulkarni • Sidharth Sood • Xiaoya Yang

2. System Objective

7. Internal Block Diagram of IIR

8. Protocol for receiving input samples • Input samples should be qualified with a load signal (LD_X here) • Samples cannot be accepted faster than once every 6 clock cycles • (at 200MHz system CLK, about 33 M samples processed per second)

9. Implementation Targets • System clock = 200 MHz • Total system power <= 0.25 W • Target technology = AMI 0.6u C5N • Output Load of 20 fF Division of Work • Meghana Khadkikar - REG A, 2to1 MUX, Post extraction Sims, Power Analysis • Parul Apan - Top level integration, Control Module, D-Flop • Rohini Kulkarni - Full Adder • Sidharth Sood - Basic gates • Xiaoya Yang - REG B

10. TOP LEVEL

11. Top-Level Schematic

12. Impulse response - input

13. Impulse response - output

14. Step response - input

15. Step response - output

16. Top-Level - Layout

17. Top-Level - DRC Report

18. Top-Level - LVS Report

19. Step response - Post-extraction

20. Impulse response – Post extraction

21. Power Analysis – Pre Extraction

22. Power Analysis – Post Extraction

23. Control Module

24. Control Module

25. Control Module - Schematic

26. Control module

27. Control module - Layout

28. Control Module - DRC

29. Control module - LVS

30. Control module – Post-extraction

31. D-Flop

32. D-Flop Schematic

33. D-Flop Calculations • Initial estimates: • Max setup time ~ 600ps • Clock to Q delay ~ 400ps • Hold time ~ 150ps • On this basis, the values for following constants were calculated as: • Ratio = 1.775 • Cgin = 10.86 x WN fF (assuming each nand would drive 3 nands) • WN = 2.84u; WP = 4.437u • Final Values: • Actual value for ‘Ratio’ was found from parametric analysis keeping WN = 3u • It came out to be 1.8  WP = 5.4u

34. D-Flop

35. D-Flop- Setup Characterization

36. D-Flop Layout

37. D-Flop DRC

38. D-Flop LVS

39. D-Flop – Post-extraction

40. Full Adder

41. Truth Table of Full_Adder

42. FULL ADDER SCHEMATIC Full Adder -Schematic

43. Hand Calculations • AND2: • Tphl=Tplh =1ns • Wn=37u Wp=2.7u ,Wni= 2.7u Wpi=1.5u • OR2 • Tphl=Tplh=1ns • Wn=1.5u Wp=2.7u , Wni=2.55u Wpi=4.5u • XOR2: • Tphl=Tplh =1.5ns • Wn=1.65u Wp=3u ,Wni= 2.7u Wpi=1.5u\ • Post extraction delay: Tphl=Tplh=1ns

44. Full Adder

45. Full Adder - Layout

46. Full Adder - DRC

47. LVS report • Like matching is enabled. • Net swapping is enabled. • Using terminal names as correspondence points. • Compiling Diva LVS rules... • Net-list summary for /home/sood5306/PROJECT_166/work/rohini/LVS/layout/netlist • count • 26 nets • 7 terminals • 21 pmos • 21 nmos

48. Net-list summary for /home/sood5306/PROJECT_166/work/rohini/LVS/schematic/netlist count 26 nets 7 terminals 21 pmos 21 nmos Terminal correspondence points 1 Ain 2 Bin 3 Cin 4 Cout 5 Sum 6 gnd! 7 vdd!

49. The net-lists match. layout schematic instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 42 42 total 42 42

50. un-matched 0 0 merged 0 0 pruned 0 0 active 26 26 total 26 26 terminals un-matched 0 0 matched but different type 2 2 total 7 7