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CPU 1

Main Memory. CPU 1. IRQ. FSB Controller. CPU 2. IRQ. BSB Controller. CPU n. IRQ. Expandable Device Bus. Keyboard. Interrupt Controller. Mouse. Console. DMA. Mentat Instruction (32 bits with variable addressing length). Explanation of opcodes.

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CPU 1

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  1. Main Memory CPU1 IRQ FSB Controller CPU2 IRQ BSB Controller CPUn IRQ Expandable Device Bus Keyboard Interrupt Controller Mouse Console DMA

  2. Mentat Instruction (32 bits with variable addressing length) Explanation of opcodes.

  3. Simulator Instructions (stored in memory in little-endian order) Opcodes hlt = 0x00000000, // 0000 000 mov = 0x02000000, // 0000 001 add = 0x04000000, // 0000 010 sub = 0x06000000, // 0000 011 mul = 0x08000000, // 0000 100 div = 0x0A000000, // 0000 101 cmp = 0x0C000000, // 0000 110 and = 0x0E000000, // 0000 111 or = 0x10000000, // 0001 000 xor = 0x12000000, // 0001 001 not = 0x14000000, // 0001 010 shl = 0x16000000, // 0001 011 shr = 0x18000000, // 0001 100 tss = 0x1A000000, // 0001 101 swp = 0x1C000000, // 0001 110 neg = 0x1E000000, // 0001 111 jmp = 0x20000000, // 0010 000 jeq = 0x22000000, // 0010 001 jne = 0x24000000, // 0010 010 jl = 0x26000000, // 0010 011 jg = 0x28000000, // 0010 100 jle = 0x2A000000, // 0010 101 jge = 0x2C000000, // 0010 110 cmjnz = 0x2E000000, // 0010 111 nop = 0x30000000, // 0011 000 jov = 0x32000000, // 0011 001 ret = 0x34000000, // 0011 010 prc = 0x36000000, // 0011 011 int = 0x38000000, // 0011 100 pow = 0x3A000000, // 0011 101 push = 0x3C000000, // 0011 110 pop = 0x3E000000, // 0011 111 movb = 0x40000000, // 0100 000 addb = 0x42000000, // 0100 001 subb = 0x44000000, // 0100 010 mulb = 0x46000000, // 0100 011 divb = 0x48000000, // 0100 100 cmpb = 0x4A000000, // 0100 101 andb = 0x4C000000, // 0100 110 orb = 0x4E000000, // 0100 111 xorb = 0x50000000, // 0101 000 notb = 0x52000000, // 0101 001 shlb = 0x54000000, // 0101 010 shrb = 0x56000000, // 0101 011 tssb = 0x58000000, // 0101 100 swpb = 0x5A000000, // 0101 101 negb = 0x5C000000, // 0101 110 pushb = 0x5E000000, // 0101 111 popb = 0x60000000, // 0110 000 getb = 0x62000000, // 0110 001 setf = 0x64000000, // 0110 010 getf = 0x66000000, // 0110 011 clrf = 0x68000000, // 0110 100 loop = 0x6A000000, // 0110 101 mcp = 0x6C000000, // 0110 110 mcpb = 0x6E000000, // 0110 111 cmjz = 0x70000000, // 0111 000 prcx = 0x72000000, // 0111 001 retx = 0x74000000, // 0111 010 scp = 0x76000000, // 0111 011 sscan = 0x78000000, // 0111 100 scmp = 0x7A000000, // 0111 101 fill = 0x7C000000, // 0111 110 fillb = 0x7E000000, // 0111 111 atoi = 0x80000000, // 1000 000 atou = 0x82000000, // 1000 001 facos = 0x84000000, // 1000 010 fadd = 0x86000000, // 1000 011 fasin = 0x88000000, // 1000 100 fatan = 0x8A000000, // 1000 101 fceil = 0x8C000000, // 1000 110 fcos = 0x8E000000, // 1000 111 fdiv = 0x90000000, // 1001 000 fexp = 0x92000000, // 1001 001 ffloor = 0x94000000, // 1001 010 flog = 0x96000000, // 1001 011 flog10 = 0x98000000, // 1001 100 fmul = 0x9A000000, // 1001 101 fpow = 0x9C000000, // 1001 110 fsin = 0x9E000000, // 1001 111 fsqrt = 0xA0000000, // 1010 000 fsub = 0xA2000000, // 1010 001 ftan = 0xA4000000, // 1010 010 ftoi = 0xA6000000, // 1010 011 ftoa = 0xA8000000, // 1010 100 itoa = 0xAA000000, // 1010 101 itof = 0xAC000000, // 1010 110 rmcp = 0xAE000000, // 1010 111 rsany = 0xB0000000, // 1011 000 rscp = 0xB2000000, // 1011 001 rsscan = 0xB4000000, // 1011 010 sany = 0xB6000000, // 1011 011 atof = 0xB8000000, // 1011 100 strlen = 0xBA000000, // 1011 101 strstr = 0xBC000000, // 1011 110 udiv = 0xBE000000, // 1011 111 jinf = 0xC0000000, // 1100 000 umul = 0xC2000000, // 1100 001 jnan = 0xC4000000, // 1100 010 utoa = 0xC6000000, // 1100 011 frtod = 0xC8000000, // 1100 100 fdtor = 0xCA000000, // 1100 101 ftou = 0xCC000000, // 1100 110 rmcpb = 0xCE000000, // 1100 111 rstrstr= 0xD0000000, // 1101 000 save = 0xD2000000, // 1101 001 rest = 0xD4000000, // 1101 010 savea = 0xD6000000, // 1101 011 resta = 0xD8000000, // 1101 100

  4. Simulator Instructions (stored in memory in big-endian order) Left Registers r0 = 0x00000000, // xxxx xxx0 0000 0 r1 = 0x00080000, // xxxx xxx0 0000 1 r2 = 0x00100000, // xxxx xxx0 0001 0 r3 = 0x00180000, // xxxx xxx0 0001 1 r4 = 0x00200000, // xxxx xxx0 0010 0 r5 = 0x00280000, // xxxx xxx0 0010 1 r6 = 0x00300000, // xxxx xxx0 0011 0 r7 = 0x00380000, // xxxx xxx0 0011 1 r8 = 0x00400000, // xxxx xxx0 0100 0 r9 = 0x00480000, // xxxx xxx0 0100 1 r10 = 0x00500000, // xxxx xxx0 0101 0 r11 = 0x00580000, // xxxx xxx0 0101 1 r12 = 0x00600000, // xxxx xxx0 0110 0 r13 = 0x00680000, // xxxx xxx0 0110 1 r14 = 0x00700000, // xxxx xxx0 0111 0 r15 = 0x00780000, // xxxx xxx0 0111 1 r16 = 0x00800000, // xxxx xxx0 1000 0 r17 = 0x00880000, // xxxx xxx0 1000 1 r18 = 0x00900000, // xxxx xxx0 1001 0 r19 = 0x00980000, // xxxx xxx0 1001 1 r20 = 0x00A00000, // xxxx xxx0 1010 0 r21 = 0x00A80000, // xxxx xxx0 1010 1 r22 = 0x00B00000, // xxxx xxx0 1011 0 r23 = 0x00B80000, // xxxx xxx0 1011 1 r24 = 0x00C00000, // xxxx xxx0 1100 0 r25 = 0x00C80000, // xxxx xxx0 1100 1 r26 = 0x00D00000, // xxxx xxx0 1101 0 r27 = 0x00D80000, // xxxx xxx0 1101 1 r28 = 0x00E00000, // xxxx xxx0 1110 0 r29 = 0x00E80000, // xxxx xxx0 1110 1 r30 = 0x00F00000, // xxxx xxx0 1111 0 r31 = 0x00F80000, // xxxx xxx0 1111 1 r32 = 0x01000000, // xxxx xxx1 0000 0 r33 = 0x01080000, // xxxx xxx1 0000 1 r34 = 0x01100000, // xxxx xxx1 0001 0 r35 = 0x01180000, // xxxx xxx1 0001 1 r36 = 0x01200000, // xxxx xxx1 0010 0 r37 = 0x01280000, // xxxx xxx1 0010 1 r38 = 0x01300000, // xxxx xxx1 0011 0 r39 = 0x01380000, // xxxx xxx1 0011 1 r40 = 0x01400000, // xxxx xxx1 0100 0 r41 = 0x01480000, // xxxx xxx1 0100 1 r42 = 0x01500000, // xxxx xxx1 0101 0 r43 = 0x01580000, // xxxx xxx1 0101 1 r44 = 0x01600000, // xxxx xxx1 0110 0 r45 = 0x01680000, // xxxx xxx1 0110 1 r46 = 0x01700000, // xxxx xxx1 0111 0 r47 = 0x01780000, // xxxx xxx1 0111 1 r48 = 0x01800000, // xxxx xxx1 1000 0 r49 = 0x01880000, // xxxx xxx1 1000 1 r50 = 0x01900000, // xxxx xxx1 1001 0 OSLimit = 0x01980000, // xxxx xxx1 1001 1(osl)* memBase = 0x01A00000, // xxxx xxx1 1010 0(mbs)* memLimit = 0x01A80000, // xxxx xxx1 1010 1(mlmt)* heapPointer = 0x01B00000, // xxxx xxx1 1011 0(hp)* programCounter = 0x01B80000, // xxxx xxx1 1011 1(pc) auxiliary = 0x01C00000, // xxxx xxx1 1100 0(aux) interrupt = 0x01C80000, // xxxx xxx1 1100 1(int) interruptMask = 0x01D00000, // xxxx xxx1 1101 0(msk) stackPointer = 0x01D80000, // xxxx xxx1 1101 1(sp) basePointer = 0x01E00000, // xxxx xxx1 1110 0(bp) pageTableAddr = 0x01E80000, // xxxx xxx1 1110 1(pta) * counter = 0x01F00000, // xxxx xxx1 1111 0(ctr) flags = 0x01F80000, // xxxx xxx1 1111 1(flg) * Requires supervisor bit set to write

  5. Simulator Instructions (stored in memory in big-endian order) Left Addressing Modes Unused = 0x00000000, // xxxx xxxx xxxx x000 00 RegisterDirect = 0x00000000, // xxxx xxxx xxxx x000 01 r1 RegisterIndirect = 0x00020000, // xxxx xxxx xxxx x000 10 [r1] RegisterIndirectPostIncrement = 0x00040000, // xxxx xxxx xxxx x000 11 [r1+] RegisterIndirectPostDecrement = 0x00060000, // xxxx xxxx xxxx x001 00 [r1-] RegisterIndirectPreIncrement = 0x00080000, // xxxx xxxx xxxx x001 01 [+r1] RegisterIndirectPreDecrement = 0x000A0000, // xxxx xxxx xxxx x001 10 [-r1] RegisterIndirectOffset = 0x000C0000, // xxxx xxxx xxxx x001 11 [r1+4] RegisterIndirectPlusRegister = 0x000E0000, // xxxx xxxx xxxx x010 00 [r1+r2] MemoryDirect = 0x00100000, // xxxx xxxx xxxx x010 01 [r1-r2] MemoryIndirect = 0x00120000, // xxxx xxxx xxxx x010 10 [Addr] MemoryIndirectPostIncrement = 0x00140000, // xxxx xxxx xxxx x010 11 #[Addr+] MemoryIndirectPostDecrement = 0x00160000, // xxxx xxxx xxxx x011 00 #[Addr-] MemoryIndirectPreIncrement = 0x00180000, // xxxx xxxx xxxx x011 01 #[+Addr] MemoryIndirectPreDecrement = 0x001A0000, // xxxx xxxx xxxx x011 10 #[-Addr] MemoryIndirectPlusRegister = 0x001C0000, // xxxx xxxx xxxx x011 11 #[Addr]

  6. Simulator Instructions (stored in memory in big-endian order) Right Registers r0 = 0x00000000, // xxxx xxxx xxxx xxxx xx00 0000 r1 = 0x00000100, // xxxx xxxx xxxx xxxx xx00 0001 r2 = 0x00000200, // xxxx xxxx xxxx xxxx xx00 0010 r3 = 0x00000300, // xxxx xxxx xxxx xxxx xx00 0011 r4 = 0x00000400, // xxxx xxxx xxxx xxxx xx00 0100 r5 = 0x00000500, // xxxx xxxx xxxx xxxx xx00 0101 r6 = 0x00000600, // xxxx xxxx xxxx xxxx xx00 0110 r7 = 0x00000700, // xxxx xxxx xxxx xxxx xx00 0111 r8 = 0x00000800, // xxxx xxxx xxxx xxxx xx00 1000 r9 = 0x00000900, // xxxx xxxx xxxx xxxx xx00 1001 r10 = 0x00000A00, // xxxx xxxx xxxx xxxx xx00 1010 r11 = 0x00000B00, // xxxx xxxx xxxx xxxx xx00 1011 r12 = 0x00000C00, // xxxx xxxx xxxx xxxx xx00 1100 r13 = 0x00000D00, // xxxx xxxx xxxx xxxx xx00 1101 r14 = 0x00000E00, // xxxx xxxx xxxx xxxx xx00 1110 r15 = 0x00000F00, // xxxx xxxx xxxx xxxx xx00 1111 r16 = 0x00001000, // xxxx xxxx xxxx xxxx xx01 0000 r17 = 0x00001100, // xxxx xxxx xxxx xxxx xx01 0001 r18 = 0x00001200, // xxxx xxxx xxxx xxxx xx01 0010 r19 = 0x00001300, // xxxx xxxx xxxx xxxx xx01 0011 r20 = 0x00001400, // xxxx xxxx xxxx xxxx xx01 0100 r21 = 0x00001500, // xxxx xxxx xxxx xxxx xx01 0101 r22 = 0x00001600, // xxxx xxxx xxxx xxxx xx01 0110 r23 = 0x00001700, // xxxx xxxx xxxx xxxx xx01 0111 r24 = 0x00001800, // xxxx xxxx xxxx xxxx xx01 1000 r25 = 0x00001900, // xxxx xxxx xxxx xxxx xx01 1001 r26 = 0x00001A00, // xxxx xxxx xxxx xxxx xx01 1010 r27 = 0x00001B00, // xxxx xxxx xxxx xxxx xx01 1011 r28 = 0x00001C00, // xxxx xxxx xxxx xxxx xx01 1100 r29 = 0x00001D00, // xxxx xxxx xxxx xxxx xx01 1101 r30 = 0x00001E00, // xxxx xxxx xxxx xxxx xx01 1110 r31 = 0x00001F00, // xxxx xxxx xxxx xxxx xx01 1111 r32 = 0x00002000, // xxxx xxxx xxxx xxxx xx10 0000 r33 = 0x00002100, // xxxx xxxx xxxx xxxx xx10 0001 r34 = 0x00002200, // xxxx xxxx xxxx xxxx xx10 0010 r35 = 0x00002300, // xxxx xxxx xxxx xxxx xx10 0011 r36 = 0x00002400, // xxxx xxxx xxxx xxxx xx10 0100 r37 = 0x00002500, // xxxx xxxx xxxx xxxx xx10 0101 r38 = 0x00002600, // xxxx xxxx xxxx xxxx xx10 0110 r39 = 0x00002700, // xxxx xxxx xxxx xxxx xx10 0111 r40 = 0x00002800, // xxxx xxxx xxxx xxxx xx10 1000 r41 = 0x00002900, // xxxx xxxx xxxx xxxx xx10 1001 r42 = 0x00002A00, // xxxx xxxx xxxx xxxx xx10 1010 r43 = 0x00002B00, // xxxx xxxx xxxx xxxx xx10 1011 r44 = 0x00002C00, // xxxx xxxx xxxx xxxx xx10 1100 r45 = 0x00002D00, // xxxx xxxx xxxx xxxx xx10 1101 r46 = 0x00002E00, // xxxx xxxx xxxx xxxx xx10 1110 r47 = 0x00002F00, // xxxx xxxx xxxx xxxx xx10 1111 r48 = 0x00003000, // xxxx xxxx xxxx xxxx xx11 0000 r49 = 0x00003100, // xxxx xxxx xxxx xxxx xx11 0001 r50 = 0x00003200, // xxxx xxxx xxxx xxxx xx11 0010 OSLimit = 0x00003300, // xxxx xxxx xxxx xxxx xx11 0011(osl)* memBase = 0x00003400, // xxxx xxxx xxxx xxxx xx11 0100(mbs)* memLimit = 0x00003500, // xxxx xxxx xxxx xxxx xx11 0101(mlmt)* heapPointer = 0x00003600, // xxxx xxxx xxxx xxxx xx11 0110(hp)* programCounter = 0x00003700, // xxxx xxxx xxxx xxxx xx11 0111(pc) auxiliary = 0x00003800, // xxxx xxxx xxxx xxxx xx11 1000(aux) interrupt = 0x00003900, // xxxx xxxx xxxx xxxx xx11 1001(int) interruptMask = 0x00003A00, // xxxx xxxx xxxx xxxx xx11 1010(msk) stackPointer = 0x00003B00, // xxxx xxxx xxxx xxxx xx11 1011(sp) basePointer = 0x00003C00, // xxxx xxxx xxxx xxxx xx11 1100(bp) pageTableAddr = 0x00003D00, // xxxx xxxx xxxx xxxx xx11 1101(pta)* counter = 0x00003E00, // xxxx xxxx xxxx xxxx xx11 1110(ctr) flags = 0x00003F00, // xxxx xxxx xxxx xxxx xx11 1111(flg) * Requires supervisor bit set to write

  7. Simulator Instructions (stored in memory in big-endian order) Right Addressing Modes Immediate = 0x00000000, // xxxx xxxx xxxx xxxx xxxx xxxx 0000 0 Addr RegisterDirect = 0x00000080, // xxxx xxxx xxxx xxxx xxxx xxxx 0000 1 r1 RegisterIndirect = 0x00000100, // xxxx xxxx xxxx xxxx xxxx xxxx 0001 0 [r1] RegisterIndirectPostIncrement = 0x00000180, // xxxx xxxx xxxx xxxx xxxx xxxx 0001 1 [r1+] RegisterIndirectPostDecrement = 0x00000200, // xxxx xxxx xxxx xxxx xxxx xxxx 0010 0 [r1-] RegisterIndirectPreIncrement = 0x00000280, // xxxx xxxx xxxx xxxx xxxx xxxx 0010 1 [+r1] RegisterIndirectPreDecrement = 0x00000300, // xxxx xxxx xxxx xxxx xxxx xxxx 0011 0 [-r1] RegisterIndirectOffset = 0x00000380, // xxxx xxxx xxxx xxxx xxxx xxxx 0011 1 [r1+4] RegisterIndirectPlusRegister = 0x00000400, // xxxx xxxx xxxx xxxx xxxx xxxx 0100 0 [r1+r2] MemoryDirect = 0x00000480, // xxxx xxxx xxxx xxxx xxxx xxxx 0100 1 [r1-r2] MemoryIndirect = 0x00000500, // xxxx xxxx xxxx xxxx xxxx xxxx 0101 0 [Addr] MemoryIndirectPostIncrement = 0x00000580, // xxxx xxxx xxxx xxxx xxxx xxxx 0101 1 #[Addr+] MemoryIndirectPostDecrement = 0x00000600, // xxxx xxxx xxxx xxxx xxxx xxxx 0110 0 #[Addr-] MemoryIndirectPreIncrement = 0x00000680, // xxxx xxxx xxxx xxxx xxxx xxxx 0110 1 #[+Addr] MemoryIndirectPreDecrement = 0x00000700, // xxxx xxxx xxxx xxxx xxxx xxxx 0111 0 #[-Addr] MemoryIndirectPlusRegister = 0x00000780, // xxxx xxxx xxxx xxxx xxxx xxxx 0111 1 #[Addr]

  8. Flags trap sign zero carry Infinity paging on supervisor overflow paging level paging level Invalid Number mask interrupts check heap vs stack paging 256 (not 4096)

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