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P3K Team Meeting #15

P3K Team Meeting #15. Stephen Guiwits Dean Palmer Ernest Croner Team Meeting #15 -- 126 Cahill October 29, 2009. P3K Electronics Agenda. RTC Electronics (Computer Room) JPL Caltech Active Mirror Electronics (Cass Cage/AO Lab) Xinetics GenIII Integration and Test

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P3K Team Meeting #15

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  1. P3K Team Meeting #15 Stephen Guiwits Dean Palmer Ernest Croner Team Meeting #15 -- 126 Cahill October 29, 2009

  2. P3K Electronics Agenda • RTC Electronics (Computer Room) • JPL • Caltech • Active Mirror Electronics (Cass Cage/AO Lab) • Xinetics GenIII Integration and Test • Driver  Electronics Interfaces • Active Mirror Cabling • Active Mirror Communications • The near future

  3. RTC Electronics

  4. RTC Electronics • PC 0 – 9 (Telemetry) • All components installed • Rack Mounted • Cabled (JPL Only) • Each machine kickstarted • Suse Enterprise Linux 10 (non real-time) • Actively using for software development (JPL Only) • Suse Kickstart DVD • JPL version completed • Custom RPMS built and tested • 2 disks architecture • Disk 1 = Base + patches • Disk 2 = custom scripts and RPM’s • Require two versions (JPL/Caltech) • Requires custom kernel patch to see both graphic cards

  5. RTC Electronics • Optical Splitter tested. Able to get full frames to all GPU’s • Quadrics High Speed Network Switch • Installed and configured • Suse 10 Linux driver installed • Does not work with Real-Time Linux. Quadrics went out of business. We’re currently looking for solutions • RAID System • Configured for throughput optimization • RAID 0 • Two partitions • High Speed data • All other data • Gigabit Private Ethernet Switch • Each PC is able to communicate over the private ethernet • Separate from the Quadrics High Speed Switch

  6. RTC Electronics • KVM Switch • Convenience • Allows for graphical access to each machine while working on the racks • Helpful while debugging an issue with any one of the 10 machines located in the racks

  7. RTC Electronics Development Racks Located at JPL Room: 306-130C PC 0 – 8 RAID System KVM Switch Quadrics High Speed Switch 16 Port Gigabit Ethernet Switch Optical Splitter 7

  8. RTC Electronics • Production Racks (Caltech) • Located in Room 17b Cahill Center • Machines mounted in racks • 2 machines kickstarted for initial testing of Caltech Kickstart • JPL System Administrators are still working on the final version of the kickstart 8

  9. RTC Electronics 9

  10. DM Integration and Test

  11. DM Driver Integration and Test • July 2009 :: Xinetics :: Devens, Massachusetts • Hardware required • Xinetics Gen III Mirror Electronics • (4U GenIII chassis + 1U fan tray) * 8 • Perle IOLAN STS Terminal Server • 8 RJ-45  9 pin serial adapters • 8 RJ-45 cables • Custom PCB interface boards • Required to cable the mirror • Bud Industry 30U Rack (2) • Pulizzi IPC 3401 (2) • Dell Precision T7400 Computer • Associated cabling and interfaces required for integration and test

  12. DM Driver Integration and Test • Hardware

  13. DM Driver Integration and Test • Software • Initial non-high speed software written • Communicates via serial terminal server • PC  ethernet  terminal server  RJ-45  9 pin  driver • Successful command and control of all 8 driver • Command set • Power up • Power down • Put driver in proper mode (Normal or Test) • Clear faults on the drive (Xinetics feature) • Mute the drivers • Drive actuator values • Drive bias value • Read back voltage table (needs tweaking) • Read status table (needs tweaking)

  14. DM Driver Integration and Test • Testing Results • Mirror had some issues. Jenny covered that during the optical bench presentation • PCB boards mapped incorrectly. Still able to move every actuator to bias levels • Able to re-wire some of the cables so we can continue to use the boards while a final design is being worked on • Cables already sent out and modified • Software worked upon arrival. Little changes were required to deal with undocumented behavior of the GenIII driver API • Optical results were covered in the optical bench presentation

  15. Active Mirror Cabling

  16. Active Mirror Cabling • 2 PCB Designs • Driver Interface Board (DIB) (x16) • 2 per chassis • Board routes all actuators, grounds, and bias from driver 50 pin connector to 260 pin connector • Mirror Interface Board (MIB) (x16) • Board routes actuators, bias, and ground signal from 260-pin connector to 62 and 44 pin connectors • 2 pin connectors are used to daisy chain bias and grounds to each PCB as needed

  17. Active Mirror Cabling High Level Block Diagram

  18. Active Mirror Cabling Hypertronics N Series Connectors

  19. Active Mirror Cabling Computer Rendering of the Mirror Interface Box

  20. Active Mirror Cabling • Remaining costs to complete the cables and interface boards • Procurements • Hypertronics (34 plugs&sockets)  $29,000DM • cables (17)                                    $70,100 ($3800 per cable +tx) • Driver interface boards (17)                 $1300 • Rack mounting panels (8)                    $800 • Driver-rack interface ribbon cables       $1200 • IDC Connectors for PCB                     $500 • DSUB connectors for PCB                    $1050 • DSUB mating connectors                       $1150 • Back shells for DSUB connectors            $700 • Mirror interface boards (17)                  $1300 • Bench interface box (1)                         $1500  --------------- $108,600

  21. Active Mirror Cabling • Remaining costs to complete the cables and interface boards • Labor (in days) • Mirror interface board design                  1 Weeks • Driver interface board design                  3 Weeks • Mirror interface cable design                   4 Weeks • Procurements                                        3 Days         • Rack panel mech. design                        1 Day • Bench box mech. design                         4 Days • Bench interface box wiring                      6 Weeks ------------------------ 15 Weeks 1 Day

  22. Active Mirror Cabling • Near-term milestones • MIB and DIB designed finished by November 26, 2009 • 17 custom cables ordered by November 26, 2009 • Cables have a long lead time • Cables can be started without the final connectors available

  23. Active Mirror Communications

  24. Active Mirror Communications

  25. DM High-Speed Data Link Progress to date • Created a CMC Carrier Board hardware requirements specification • CMC Carrier Board Circuit design and schematic completed. • CMC Carrier Board PCB layout begun. • Component placement is almost complete. • Most of the individual circuit blocks are wired. • During the component placement, I found that we’re not able to fit all the connectors on a 6U VME card without greatly increasing the complexity of the PCB layout (blind vias, increase layer count, etc.). • Looked at a few mitigation options: • Separate board designs for LODM and HODM • Piggy-back board with connectors for HODM • Wires from board to enclosure boundary • Separate board designs is the best option for signal integrity and board complexity. Much will be shared between the two designs. • Selected a COTS cable/connector combination for the interface to the Xinetics chassis. • This requires a small adapter board at the Xinetics side • Adapter board design is nearly complete.

  26. DM High-Speed Data Link FPGA CMC Carrier Board FPGA Progress • Began initial FPGA development. • Simulated flow of data through the FPGA from the serial Front Panel Data Port input to the Xinetics SOR422-U outputs. • Still need to work out a minor bug. • Need to enhance the state machine for the data input. • Need to add inter-actuator checking algorithm. • Need to add support for LODM. • Need to add test mode.

  27. DM High-Speed Data Link Completion Forecast Forecast • November • Complete HODM Carrier Board PCB layout • Design review November 10, 2009 • Receive assembled boards. • Complete preliminary FPGA design. • Begin board testing. • December • Create Carrier Board FPGA design specification. • Complete HODM Carrier Board testing. • Complete LODM Carrier Board PCB layout.

  28. DM High-Speed Data Link Completion Forecast Forecast (cont.) • January • Complete Carrier Board FPGA design. • Receive assembled LODM Carrier Cards. • Test LODM Carrier Cards

  29. The near future • Build up RTC racks at Caltech • Complete work on Caltech Suse Kickstart • Incorporate new kernel findings into every verison of the kickstart • Work on Real-Time Linux with Quadrics • Build up DM racks at Caltech • Test the DM when it arrives from Xinetics • Measure power consumption of drivers to help determine proper cooling method • Move motion control and acquisition hardware from JPL to Caltech for development and testing • Move AO racks down from Palomar. They have been modified with cassegrain cage mounting hardware

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