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Chapter 5

Chapter 5. Number Representation and Arithmetic Circuits. Objectives. Know how numbers are represented in computers Be introduced to the circuits used to perform arithmetic operations Be aware of performance issues in large circuits Know VHDL to specify arithmetic circuits. Variables.

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Chapter 5

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  1. Chapter 5 Number Representation and Arithmetic Circuits

  2. Objectives • Know how numbers are represented in computers • Be introduced to the circuits used to perform arithmetic operations • Be aware of performance issues in large circuits • Know VHDL to specify arithmetic circuits

  3. Variables • Variables to represent the state of a switch or other condition • 010 convenient to think of as 2 but really means switches 1 and 3 off and switch 2 on • Variables to represent numbers

  4. Basic Concepts • Bit – One Binary Digit • Nibble – Four Bits • Byte – Eight Bits • LSB – Least Significant Bit • MSB – Most Significant Bit • Octal – 1101 1001 = 331 octal • Hexadecimal 1101 1001 = D9 hex 1011 1001

  5. Integers • Unsigned • Positional number representation • Convert positive integer decimal to unsigned binary by repetitively dividing by 2 • If remainder is 1 bit is 1 • Else bit is 0 Convert 857 to Binary 857/2 = 428 r1 1 LSB 428/2 = 214 r0 0 214/2 = 107 r0 0 107/2 = 53 r1 1 53/2 = 26 r1 1 26/2 = 13 r0 0 13/2 = 6 r1 1 6/2 = 3 r0 0 3/2 = 1 r1 1 1/2 = 0 r1 1 MSB 1101011001 base 2

  6. Addition of Unsigned Binary Carry 1 1 1 0 X = 0 1 1 1 1 Y = 0 1 0 1 0 Sum = 1 1 0 0 1 • Truth Table A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

  7. Design Logic to Add 2 5 bit Binary Numbers • Truth Table • x4 x3 x2 x1 x0 y4 y3 y2 y1 y0 Sum • Method is to Consider each pair separately

  8. XOR 2 Input Truth Table A B XOR 0 0 0 0 1 1 1 0 1 1 1 0 • 3 Input Truth Table • A B C XOR • 0 0 0 • 0 0 1 • 0 1 0 • 0 1 1 • 1 0 0 • 1 0 1 • 1 1 0 • 1 1 1 0 1 1 0 1 0 0 1

  9. XOR Gate • Generates Modulo-2 sum of its inputs • Output is equal to • 1 if an odd number of inputs have the value of 1s • 0 otherwise • Sometimes referred to as the ODD function

  10. Signed Binary Integers • Sign and Magnitude • MSB becomes the sign bit • MSB of number is n-1 • Not well suited for use in binary computers

  11. 1’s Complement • Negative numbers created by subtraction • N bit negative number K is generated by subtracting its equivalent positive number P from 2n-1 • K = (2n-1) – P • -5 1111 – 0101 = 1010 • -3 1111 – 0011 = 1100 • Basically complement the absolute value of the number • Has some drawbacks too

  12. 2’s Complement • Negative numbers created by subtracting from 2n Negative number K is obtained by subtracting its equivalent positive number P from 2n • K = 2n – P • -5 10000 – 0101 = 1011 • -3 10000 – 0011 = 1101 • Add 1 to number’s 1’s complement • 2’s complement number are obtained in this manner • Examine bits from right, copy all bits that are 0 and the first bit that is 1, complement the rest

  13. 2’s Complement • - 5 0101 = 1011 • -3 0011 = 1101 • -6 0110 = 1010

  14. Fixed Point • B = bn-1bn-2…b1b0.b-1b-2…b-k • 1011.101 • 1x23 + 0x22 + 1x21 + 1x20 + 1x2-1 + 0x2-2 + 1x2-3 • 8+2+1+0.5+0.125 • 11.625

  15. 32 bits S E M Sign 8-bit 23 bits of mantissa + 0 denotes excess-127 – 1 denotes exponent (a) Single precision 64 bits S M E Sign 11-bit excess-1023 52 bits of mantissa exponent (b) Double precision Floating Point • Sign, Mantissa, and Exponent

  16. Single Precision Floating-Point Format • Exponent in excess-127 format • Exponent = E – 127 • Exponent always positive integer • E = 0 is zero • E = 255 is infinity • Normal range of E –126 to 127 or an • E of 1 to 254 • Mantissa field 23 bits • Value +/-1.M x 2E-127

  17. Single Precision Floating-Point Format • 00101011101110011011110010011000 • 0 = Positive number • 01010111 = 87 -> 87 - 127 = -40 • 01110011011110010011000 = 3783832 • 1.3783832 x 2-40

  18. Double Precision Floating-Point Format • Exponent in excess-1023 format • Exponent = E – 1023 • Exponent always positive integer • E = 0 is zero • E = 2047 is infinity • Normal range of E –1022 to 1023 or an • E of 1 to 2046 • Mantissa field 52 bits • Value +/-1.M x 2E-127

  19. BCD – Binary Coded Decimal • Only 0-9 are used • 8 + 2 results in a carry out

  20. LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY BCD IS PORT ( X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ; END BCD ; ARCHITECTURE Behavior OF BCD IS SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ; SIGNAL Adjust : STD_LOGIC ; BEGIN Z <= ('0' & X) + Y ; Adjust <= '1' WHEN Z > 9 ELSE '0' ; S <= Z WHEN (Adjust = '0') ELSE Z + 6 ; END Behavior ;

  21. Parity • Used for error checking • Include extra bit called parity bit • Even parity – parity bit is adjusted such that the number of 1s is even • Odd parity – parity bit is adjusted such that the number of 1s is odd

  22. Parity • 1011 0110 • If • Even parity, parity bit = 1 • Odd parity, parity bit = 0 • Transmitted string • Even parity 1 1011 0110 • Odd parity 0 1011 0110

  23. Overflow • Result of arithmetic operation must fit in bits used to represent number if result does not fit an arithmetic overflow has occurred No Overflow Overflow 0110 0110 +0010 +1010 1000 10000

  24. Multiplication • Binary multiplication by 2s is a shift left • Other than 2s – Shift and Add • Other techniques exist • Consult V.C. Hamacher, Z.G. Vranesic and S.G. Zaky, Computer Organization, 5th ed. (McGraw-Hill: New York, 2002)

  25. Numbers in VHDL Code • SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) • MSB = C(1), LSB = C(3) • C <= “100” then C(1) = 1, C(3) = 0 • Appropriate for signals grouped together not numbers • SIGNAL Z : STD_LOGIC_VECTOR(1 DOWNTO 3) • MSB = Z(3), LSB = Z(1) • Z <= “100” then C(1) = 0, C(3) = 1

  26. Arithmetic in VHDL • SIGNAL X, Y, S : STD_LOGIC_VECTOR(15 DOWNTO 0); • S <= X + Y REPRESENTS a 16-bit adder • Must add • USE ieee.std_logic_signed.all;

  27. ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); Cout, Overflow : OUT STD_LOGIC ); END adder16; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum: STD_LOGIC_VECTOR(16 DOWNTO 0); BEGIN Sum <= (‘0’ & X) + Y + Cin; S <= Sum(15 DOWNTO 0); Cout <= Sum(16); Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15); END Behavior; Solution to S <= X + Y not including carry-in, carry-out, or overflow & in VHDL means concatenate One operand must have same number of bits as result – SIGNAL Using only part of a variable S <= Sum(15 DOWNTO 0);

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