Student: Khinich Fanny Instructor: Fiksman Evgeny

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory Final Stage Presentation Virtex II Pro FPGA Dynamic Reconfiguration Student: Khinich Fanny Instructor: Fiksman Evgeny Spring semester 2007

2. Abstract • Partial reconfiguration involves defining distinct portions of an FPGA design to be reconfigured while the rest of the device remains in active operation. • Active partial reconfiguration is done when the device is active.

3. Virtex II Pro Architecture Configuration Data Bits that directly define the state of programmable logic. Configuration File The internally stored file that controls the FPGA so that it performs the desired logic function.

4. Configuration of Virtex II Pro Configuration Frame The smallest number of bits that can be read or written through the configuration interfaces is one frame. Configuration Interface A logical interface through which configuration commands and data can be read and written.

5. Modular Design

6. Module-based Partial Reconfiguration Module-based Partial Reconfiguration is used when communication is needed between modules.

7. Physical Limitations For current FPGA devices, data is loaded on a column-basis, with the smallest load unit being a configuration bitstream "frame".

8. Physical Limitations • Height • Width • Horizontal placement • All logic encompassed by the width of the module are considered part of it’s "frame."

9. Physical Limitations 5. Clocking logic. 6. IOBs immediately above and below reconfigurable module. 7. IOBs on the edge of a leftmost or rightmost slice reconfigurable module.

10. Implementation details The considered physical limitations are applied on the bitstream compilation stage: ngdbuild –uc system.ucf Partial bitstream: bitgen -g ActiveReconfig:Yes …

11. The flow of the project • 1.Partial reconfiguration without processor. • 2.Partial reconfiguration using PowerPC processor. • 3. Partial reconfiguration using Microblaze processor

12. 1.System Architecture For No processor design Register1 Bus Macro Logic block Register2 Bus Macro

13. 1.Implementation

14. 1.Final Implementation

15. 2.System Architecture With PowerPC PPC405 BRAM RAM UART Controller Interface PLB OPB Reconfigurable Logic

16. 2.Implementation • 1.Bulding the system in XPS. • 2.Synthesis using Project Navigator for the top of full design.

17. 2.Implementation • Implementation of full design

18. 2.Implementation • 4.Generation of bitstream. • 5.Initialization of Brams (memory) • using command prompt : • data2mem … • 5.Download to the device.

19. 2.Modular design for system with Power PC • There was no way to place and routed reconfigurable module into design since Xilinx Tools generated the follow error: • FATAL_ERROR:Par:Portability/export/Port_Main.h:127:1.2 - This application has discovered an exceptional condition from which it cannot recover. • Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at http://www.xilinx.com/support.

20. 3.System architecture and implementation with Microblaze • The same flow was used to build system using Microblaze (soft-core processor) instead of PowerPC (hard-core processor)

21. Summary table