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A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits

A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits. Lukas Sekanina and Zdenek Vasicek. DATE’12. OUTLINE. 1. INTRODUCTION 2. POLYMORPHIC CIRCUITS 3. DIRECT EVOLUTION OF POLYMORPHIC CIRCUITS USING CGP

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A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits

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  1. A SAT-based Fitness Function for EvolutionaryOptimization of Polymorphic Circuits Lukas Sekanina and ZdenekVasicek DATE’12

  2. OUTLINE • 1.INTRODUCTION • 2. POLYMORPHIC CIRCUITS • 3. DIRECT EVOLUTION OF POLYMORPHIC CIRCUITS USING CGP • 4. PROPOSED FITNESS EVALUATION FOR POLYMORPHIC CIRCUITS • 5.RESULTS • 6. CONCLUSIONS

  3. INTRODUCTION • Polymorphic gates were described by the NASA JPL evolvable hardware group in2001 [1] • Graphene reconfigurable logic devices, discovered at IBM T. J. Watson ResearchCenter, were presented in 2010[2].

  4. INTRODUCTION

  5. POLYMORPHIC CIRCUITS • A.Polymorphic Multiplexing • In polymorphic multiplexing, we just connect the corresponding outputs of F1 and F2 by polymorphic multiplexers [5].

  6. POLYMORPHIC CIRCUITS • B.Polymorphic BDDs[5] • Terminal nodes can contain polymorphic logic functions. • Decision nodes are then implemented using standard multiplexers.

  7. POLYMORPHIC CIRCUITS • C.Evolutionary Approaches • Cartesian genetic programming (CGP)[11] can be seeded by a circuit created using polymorphic multiplexing or PolyBDDs and used to reduce the number of gates. • The method is applicable for small problem.

  8. DIRECT EVOLUTION OF POLYMORPHIC CIRCUITSUSING CGP • Genetic Algorithm flow

  9. DIRECT EVOLUTION OF POLYMORPHIC CIRCUITSUSING CGP • CGP has been developed for circuit evolution by Miller and Thompson [11], [12].

  10. DIRECT EVOLUTION OF POLYMORPHIC CIRCUITSUSING CGP • b is the number of correct output bits obtained as response for all possible assignments to the inputs • z denotes the number of gates utilized in a offspring circuit

  11. PROPOSED FITNESS EVALUATION FOR POLYMORPHICCIRCUITS • The SAT-based Equivalence Checking

  12. PROPOSED FITNESS EVALUATION FOR POLYMORPHICCIRCUITS

  13. PROPOSED FITNESS EVALUATION FOR POLYMORPHICCIRCUITS

  14. PROPOSED FITNESS EVALUATION FOR POLYMORPHICCIRCUITS

  15. RESULTS • Intel Xeon E5345 2.33 GHz • The MiniSAT 2 (version 070721) has been used as a SAT solver [18]. • Benchmark LGSynth91

  16. RESULTS

  17. RESULTS

  18. RESULTS

  19. RESULTS

  20. RESULTS

  21. CONCLUSIONS • We proposed a new CGP-based method for evolutionary optimization of polymorphic circuits. • The new CGP-based method can reduce the number of gates by 20- 40% in comparison to conventional methods.

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