Delayed Branching Explained

1. Delayed Branching Explained Winter, 2005 Print a copy of these and handout, not the old one

2. Chapter Example: Impact of Basic Static Branch Policies in Deeply Pipelined Processors Notes: Assume that Target Address is calculated at the end of 3rd stage and Branches are resolved at the end of 4th stage. Pipeline Stage: Since the processor has deeper pipeline We can name first few stages factitiously asIF, ID, TA (Target Address Calc), BC (Branch Condition Evaluation), etc

3. Exercise A3 Pipeline Example:Notes: Target Address is calculated at the end of ID stage and Branches are resolved at the end of EXE stage. Assumption: Processor has no static branch penalty reduction technique, e.g, Delayed branching, Predict Taken, etc. Note that the processor has a strategy to stall until BC is executed

4. Example Contd. (2). Case: Always Flush

5. Example Contd. (3). Case: Predict Taken

6. Example Contd. (4). Case: Predict Not Taken

7. SummarySimple Static Techniques

8. Study of MIPS 5-stage Integer Pipeline: Simple Array Copy program

9. MIPS AGGRESSIVE BRANCHING CASE (Normal Behavior of Branch in Array Copy Program)

10. Delayed Branching: Since there is always an instruction between the target and branch, hence delay.

11. Cancelled Branching: Instruction in delay slot NOT executed if branch is not taken (MIPS BEQL (Branch if Equal Likely is an Example)

12. Comparison