Topics

1. Topics • Bus interfaces. • Platform FPGAs.

2. Bus interfaces • Requirements: • High performance. • Variable signal environment. • Techniques: • Asynchronous logic. • Handshaking-oriented protocols.

3. Timing diagrams 1 0 a changing stable b Timing constraint c

4. Asynchronous logic • Distribute timing information with values. • No global clock. • Clock signal paths must have the same delay as data values.

5. adrs D Q Latching an asynchronous signal adrs adrs_ready

6. Hold time Setup time Asynchronous timing constraints • Must satisfy setup, hold times. adrs

7. requirements constraints Bus system design • Requirements: • Imposed by the other side of the system. • Constraints: • Imposed by this side of the system. a b

8. D D Q Q Views of the bus • Hardware: a b Combinational logic

9. a b D D Q Q Combinational logic Views of bus system, cont’d. • Timing diagram: x y x y

10. Bus protocols • Basic transaction: • four-cycle handshake. a b

11. Handshake machine • Each side is an FSM (possibly asynchronous): a b Go enq enq 0 1 0 1 ack ack ack

12. Basic protocols • Handshake transmits data:

13. Box 1 logic

14. Box 2 logic

15. t1 = tc1 - td1 >= tr t2 = tack1 - tc1 >= th t3 = tc2 - tack1 >= th Bus timing td1 = d stable td2 = d not stable tc1 = c rises tc2 = c falls tack1 = ack rises

16. Busses and systems • Microprocessor systems often have several busses running at different rates: CPU mem High-speed bridge I/O Low-speed

17. Basic signals in a bus

18. Bus characteristics • Physical • Connector size, etc. • Electrical • Voltages, currents, timing. • Protocol • Sequence of events.

19. Advanced transactions • Multi-cycle transfers: • Several values on one handshake. • May use implicit addressing.

20. PCI bus • Used for box-level system interconnect. • Two versions: • 33 MHz. • 66 MHz. • Supports advanced transactions.

21. PCI bus read

22. Multi-rate systems • Logic blocks running at different clock rates may communicate: • Multi-chip. • Single-chip. • Slow bus connects to fast logic. Logic 1 Logic 2 100 MHz 33 MHz

23. Metastability • Registers capturing transitioning signals may take an arbitrarily long time to settle.

24. Resynchronization • Use cascaded registers to minimize the chance of using a metastable value. d dout D Q D Q f

25. Platform FPGAs • Put all the logic for a system on one FPGA. • Requires large FPGAs plus: • Specialized logic: • I/O support; • memory interface. • CPUs.

26. Example: Virtex II Pro • Major features: • Large FPGA fabric. • High-speed I/O. • PowerPC.

27. Virtex II Pro High-speed I/O • Rocket I/O: • parallel/serial or serial/parallel transceiver. • Clock recovery circuitry. • Transceivers for multiple standards: Gigabit Ethernet, Fibre Channel, etc. • Programmable decoding features. • Interface to FPGA fabric.

28. Virtex II Pro CPUs • Up to 4 PowerPC 405s per chip: • 5 stage pipe, static branch prediction, etc. • Separate instruction, data caches. • MMU. • Timers. • Scan-based debug support.

29. PowerPC CoreConnect

30. Altera Stratix • Combines FPGA fabric, memory blocks, multipliers.

31. Stratix DSP block