Tom Newsom Vice President & General Manager SOC Business Unit May 2003

1. Agilent TechnologiesAccelerating the Future of DFT Tom NewsomVice President & General ManagerSOC Business UnitMay 2003

2. Overview • Increasing Market Momentum • Agilent Introduces the FIRST Browser for DFT • CTL: what is it, why it’s important • Design-to-Test Process • Agilent’s Power of DFT3Solution • The Future…What’s Next? NEW

3. $ Million $219 200 Orders + 90% Revenue 150 $153 $136 Loss $115 100 50 Orders ($ Billion) 0 3 2.9 -35.3 % of revenue -24.2 % of revenue 2.7 -$37 2.5 -$48 Q1 03 Q2 03 2 1.6 1.5 1.5 1.5 1.5 1.4 1.4 1.3 1.2 1 0 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 2000 2001 2002 2003 Automated Test Group Agilent Q2 ResultsOrder Momentum(Feb.-April)

4. Introducing—SmarTest PG CTL Browserthe FIRST browser for DFT NEW CTL = Core Test Language (IEEE P1450.6)

5. EDA/design database MPEG Test development 1394 ARM Core RAM MPEG High-volume Turn-on & 1394 Customer ship manufacturing characterization ARM Core RAM Diagnostics ‘Design for test’ (DFT) - general design procedures, practices and rules that allow cost-effective solutions to achieve SOC quality and fast time to market. Different colors = different tools from different companies..interfering with DFT implementation. SOC Development Process MPEG 1394 ARM Core RAM

6. EDA/design database MPEG Test development 1394 ARM Core RAM MPEG High-volume Turn-on & 1394 Customer ship manufacturing characterization ARM Core RAM Diagnostics SOC Development Process MPEG 1394 ARM Core RAM ‘Design for test’ (DFT) - general design procedures, practices and rules that allow cost-effective solutions to achieve SOC quality and fast time to market. Different colors = different tools from different companies...interfering with DFT implementation.

7. CTL allows the parts to talk with each other. SOC Development Process EDA/design database MPEG Test development 1394 ARM Core RAM MPEG MPEG 1394 Turn-on & High-volume 1394 Customer ship characterization manufacturing ARM ARM Core Core RAM RAM Diagnostics Different colors = different tools from different companies...interfering with DFT implementation.

8. CTL allows the parts to talk with each other. SOC Development Process EDA/design database MPEG Test development 1394 ARM Core RAM MPEG MPEG 1394 Turn-on & High-volume 1394 Customer ship characterization manufacturing ARM ARM Core Core RAM RAM Diagnostics Different colors = different tools from different companies...interfering with DFT implementation.

9. CTL allows the parts to talk with each other. SOC Development Process EDA/design database MPEG Test development 1394 ARM Core RAM MPEG MPEG 1394 Turn-on & High-volume 1394 Customer ship characterization manufacturing ARM ARM Core Core RAM RAM Diagnostics Different colors = different tools from different companies...interfering with DFT implementation.

10. The Answer—SmarTest PG CTL Browser NEW

11. Finally, a user-friendly interface The Answer—SmarTest PG CTL Browser

12. HTML Browser allows humans to easily use the web Darpanet a set of tools and rules to allow geeks to communicate TCP/IP standards to move packets around HTML language of the Web Internet Evolution SmarTest PG CTL Browser allows humans to implement DFT DFT a set of tools and rules to implement testability in an SOC P1500 embedded core test standard to add DFT to an SOC P1450.6 CTL emerging as language for DFT NEW DFT Evolution The Evolution of DFT - an Analogy

13. Shift { C {si[1]=#; si[0]=#; so[0]=#; so[1]=#;} V { si_m123='d[0..4] si[1] si[0]'; so_m123='so[1] so[0] q[0..2]'; clk=P; WRCK=P; }} V { clk=0; WRCK=0; sc=0; CaptureWR=1; ShiftWR=0;} V { clk=P; WRCK=P;} V { CaptureWR=0; clk=0; WRCK=0;} } } ActiveState U; Pattern Pat1 { M do_intest { d[0..4]=00000; si[0]=111000; si[1]=11110000;} M do_intest { so[0]=001X11; so[1]=111100X1; q[0..2]=001; d[0..4]=01101; si[0]=011010; si[1]=01011101;} M do_intest { so[0]=1100X1; so[1]=10110000; q[0..2]=110; d[0..4]=11001; si[0]=110010; si[1]=00011100;} M do_intest { so[0]=010001; so[1]=1X110100; q[0..2]=00X; d[0..4]=01010; si[0]=001101; si[1]=10011101;} M do_intest { d[0..4]=00000; si[0]=111000; si[1]=11110000;} M do_intest { so[0]=001X11; so[1]=111100X1; q[0..2]=001; d[0..4]=01101; si[0]=011010; si[1]=01011101;} M do_intest { so[0]=1100X1; so[1]=10110000; q[0..2]=110; d[0..4]=11001; si[0]=110010; si[1]=00011100;} M do_intest { so[0]=010001; so[1]=1X110100; q[0..2]=00X; HTML The Powerof the Browser CTL

14. Without Champions Leading End-to-End Solution, Benefits from Standards Languish Lack of tools limited STIL Adoption Agilent SmarTest PG STIL reader introduced Standard Stable / Balloted Standard Published STIL Adoption 1997 1998 1999 2000 2001 2002 2003 2004

15. S1 SmarTest PG CTL Browser EDA/Design Database End-to-end tools speed CTL adoption MPEG Test Development 1394 ARM Core RAM MPEG MPEG Customer Ship ARM1136JF-S™ core Turn-On & High-Volume 1394 1394 Tools Delivered Characterization Manufacturing ARM ARM Core Core Standard stable • DFT Compiler • TetraMAX • SoCBIST RAM RAM CTL Adoption Diagnostics 2003 2004 2005 Program to prove concept Industry Leaders Speed End-to-End Solution for maximum benefit from CTL standard NEW

17. Agilent’s Power of DFT3shortens TTM and lowers cost of test • 1. EDA/Standards • seamless design-to-test by driving partnerships and industry standards • over 3100 hours invested by partners to ensure tools are interoperable“We’re doing it so our customers don’t have to.“ • 2. Tools • fast development and learning for the SOC development process • Agilent SmarTest PG CTL browser • 3. Agilent 93000 Single Scalable Platform • with test processor per pin architecture NEW

18. Agilent’s Power of DFT3shortens TTM and lowers cost of test • 1. EDA/Standards • seamless design-to-test by driving partnerships and industry standards • over 4500 hours invested by partners to ensure tools are interoperable“We’re doing it so our customers don’t have to.“ • 2. Tools • fast development and learning for the SOC development process • Agilent SmarTest PG CTL browser • 3. Agilent 93000 Single Scalable Platform • with test processor per pin architecture NEW

19. Agilent’s Power of DFT3shortens TTM and lowers cost of test • 1. EDA/Standards • seamless design-to-test by driving partnerships and industry standards • over 4500 hours invested by partners to ensure tools are interoperable“We’re doing it so our customers don’t have to.“ • 2. Tools • fast development and learning for the SOC development process • Agilent SmarTest PG CTL browser • 3. Agilent 93000 Single Scalable Platform • with test processor per pin architecture NEW

20. Agilent’s Power of DFT3shortens TTM and lowers cost of test • 1. EDA/Standards • seamless design-to-test by driving partnerships and industry standards • over 4500 hours invested by partners to ensure tools are interoperable“We’re doing it so our customers don’t have to.“ • 2. Tools • fast development and learning for the SOC development process • Agilent SmarTest PG CTL browser • 3. Agilent 93000 Single Scalable Platform • with test processor per pin architecture NEW

21. Breaking Down the Wall Between Design and TestPower of DFT3- a history of FIRSTS FIRSTConcurrent test paper and proposal:ITC 2000 2000 FIRSTATE/EDA alliance for lower cost of test:Agilent/Synopsys FIRST ATE influenced design-to-test product:SmarTest PG FIRSTATE advocacy for P1450.3:Open standard for tester targeting paper 2001 FIRSTConcurrent test design-to-test support: SmarTest PG FIRSTIEEE 1450/1999 STIL to ATE:SmarTest PG 2002 FIRSTATE advocacy for open EDA databases:Synopsys MilkyWay FIRSTAutomatic scan compression design-to-test support:SmarTest PG FIRSTSupport for SOC DFT diagnostics:Synopsys SoCBIST FIRSTIndustry Leaders Speed End-to-End CTL Solution:Agilent/Synopsys/STM/ARM 2003 FIRSTBrowser for CTL:SmarTest PG CTL Browser NEW

22. Power of DFT3shortens TTM and lowers cost of test • 1. EDA/Standards • Agilent will make CTL the language of DFT • 2. Tools SmarTest PG CTL BrowserSee demo of complete SOC development process Semicon West Booth #10516 • 3. Agilent 93000 Single Scalable Platform • DFT solution available TODAY! New announcements & demo planned for Semicon West NEW

23. Visit Agilent at Semicon WestBooth # 10516 • Talk to industry CTL experts • Hear real customer stories • Meet with Agilent IEEE committee members • See LIVE demonstrations: • Power of DFT3solution in process TODAY!!- meet w/Agilent partners and customers - see SOC DFT process demo at Semicon West • SmarTest CTL Browser announced TODAY!!- see live demo at Semicon West • Agilent 93000 DFT solution available TODAY !!- new announcements at Semicon West

25. Appendix

26. CTL Background • IEEE P1450.6 core test language (CTL)http://grouper.ieee.org/groups/1450/index.html • an extension to IEEE 1450 standard test interface language (STIL) • utilizing IEEE P1500 embedded core test. IEEE P1500 standard for embedded core test (SECT) tells the IP core provider how to wrap cores in a standard way for testability • all necessary information for test pattern re-use • the need for test during SOC system integration • structural and test modes information to allow insertion of IP cores in an SOC design

27. Agilent 93000 Test Processor Per Pin Architecture (TPPA) - what it means for SOC DFT • Agilent 93000 TPPA enables: • Concurrent Test* • SOC DFT sets up the cores for independent operation during test, allowing them to be executed concurrently using the 93000 TPPA. Can reduce test time typically by 30-50%. • SoCBIST Diagnostics • Synopsys’ SoCBIST is a SOC DFT technique that reduces the number of vectors by 100-400x and test time by over 10x. Diagnostics of failures detected by SoCBIST requires a 93000 TPPA enabled capability called “Selective BIST Capture.” Analog Instrument JTAG Scan Port 800 MHz clock 50MHz clock BIST Control 1Gb Serial Example SOC pinout * Concurrent test requires an additional charge software license