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The Processor: Datapath & Control

22444 - Computer Architecture & Organization (1). Chapter 4:. The Processor: Datapath & Control. Stored Program Architecture. Instruction Cycle Fetch an instruction from memory Decode the instruction Get the operands Execute the instruction Where is the next instruction?

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The Processor: Datapath & Control

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  1. 22444 - Computer Architecture & Organization (1) Chapter 4: The Processor:Datapath & Control

  2. Stored Program Architecture • Instruction Cycle • Fetch an instruction from memory • Decode the instruction • Get the operands • Execute the instruction • Where is the next instruction? Program Counter (PC) Instruction Pointer (IP) • Where is the operand? Memory Instructions (Program) Opcode Operands Operands (Data) Binary Operand PC

  3. ALU CPU • Datapath • Control Unit CU Register File

  4. General-Purpose Register Organization R1 R2 R3 R4 R5 R6 R7 MUX MUX ASEL BSEL 3 x 8Decoder A B OPR ALU DSEL

  5. R1 R2 R3 R4 R5 R6 R7 MUX MUX ASEL BSEL 3 x 8Decoder A B OPR ALU DSEL General-Purpose Register Organization Examples:

  6. General-Purpose Register Organization Memory Instructions (Program) Trivial view of Opcode & Operands 00101 010 011 001 00 Operands (Data) 0000 0000 0000 0000 Examples:

  7. Memory Interface • Address / Data Buses • Read / Write Control • Bidirectional /UnidirectionalData Bus Memory Memory 24 Byte│Byte│Byte│Byte 28 Byte│Byte│Byte│Byte Addr Read Data Write Data Data

  8. Building a Datapath Write a program & compile it. Where do you want to put it? Where is the first instruction? What comes out of memory? Where to perform operation? Where are the operands? Who well tell us which reg? Where to store result? Can we save this reg to mem? • Datapath Elements Opcode │ Operands Register File 32 32 32 PC SelA Data A Addr Data B SelB Data Sel C LD Instruction Memory Data C ALU

  9. Building a Datapath • Datapath Elements At what address? Register File PC SelA Data A Addr Data Memory Data B SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU

  10. Building a Datapath How can we read it back? Register File PC SelA Data A Addr Data Memory Data B SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU

  11. Building a Datapath Finished executing instruction. Where is the next instruction? Why +4? 4 Register File PC SelA Data A Addr Data Memory MUX Data B SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU Adder

  12. Building a Datapath How can we add “immediate”? What if it is negative? 4 Opcode │ Operand │ immediate Register File PC SelA Data A Addr Data Memory MUX Data B SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU Adder Sign Extend

  13. Building a Datapath What about “JMP RelDisp”? It can be positive or negative! 4 Opcode │ Relative Displacement Register File PC SelA Data A Addr Data Memory MUX Data B MUX SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU Adder Sign Extend

  14. Building a Datapath 4 Shift Left 2 Register File PC SelA Data A Addr Data Memory MUX Data B MUX SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU Adder Adder Sign Extend

  15. Building a Datapath MUX Why the shift? 4 Shift Left 2 Register File PC SelA Data A Addr Data Memory MUX Data B MUX SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU Adder Adder Sign Extend

  16. Building a Datapath MUX 4 Shift Left 2 Why not use ALU instead of another adder? Register File PC SelA Data A Addr Data Memory MUX Data B MUX SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU Adder Adder Sign Extend

  17. Adding Control Signals to the Datapath 0 MUX 1 4 Shift Left 2 Register File PC SelA Data A Addr Data Memory 1 MUX 0 Data B 0 MUX 1 SelB Addr Data Data Sel C LD Instruction Memory Opcodeetc Data Data C ALU Adder Adder Control Unit Sign Extend Cy, Z, etc

  18. Adding Control Signals to the Datapath 0 MUX 1 4 Shift Left 2 Register File PC SelA Data A Addr Data Memory 1 MUX 0 Data B 0 MUX 1 SelB Addr Data Data Sel C LD Instruction Memory Data Data C ALU Adder Adder Control Unit Sign Extend

  19. A Simple Implementation Scheme • ALU Control 32 32 4 ALU Cntrl Cy Z 32 Cy = 1  Carry from last adder Z = 1  The result = 0 slt R1, R2, R3 ALU

  20. A Simple Implementation Scheme • Instruction Format • Arithmetic/Logic Instruction Opcode Operand(s), Address, Code 6 5 5 5 5 6 Rd = RsFunctRt 0 000000 00011 Rs Rt 00111 Rd 00101 00000 Shift 100000 Funct Register File SelA Data A Data B SelB Sel C LD Data C Example: R5 = R3+ R7

  21. A Simple Implementation Scheme • Instruction Format • Load Immediate Instruction Opcode Operand(s), Address, Code 6 5 5 16 13 001101 00000 0 Rt 00001 0000 0000 0000 1100 Immediate (Lower) Rt = Value 16 bits (can be positive or negative) Example: R1 = 12

  22. A Simple Implementation Scheme • Instruction Format • Load Memory Instruction Opcode Operand(s), Address, Code 6 5 5 16 100011 35 00100 Rs 00110 Rt 1111 1111 1111 1111 Address Rt = M [Rs + Addr] 32 bits 16 bits (can be positive or negative) Example: R6 = M [R4– 1 ]

  23. A Simple Implementation Scheme • Instruction Format • Store Memory Instruction Opcode Operand(s), Address, Code 6 5 5 16 101011 43 00111 Rs 01001 Rt 1111 1111 1111 1110 Address M [Rs + Addr] = Rt Example: M [R7– 2 ] = R9

  24. A Simple Implementation Scheme • Instruction Format • JE Operation Instruction Opcode Operand(s), Address, Code 6 5 5 16 000100 4 00001 Rs Rt 00100 1111 1111 1111 1111 Offset If Rs = Rt then PC = PC + 4*Addr PC is already incremented Example:

  25. Final Datapath Design 0 MUX 1 4 Shift Left 2 Register File Rs PC SelA Data A Rt Addr Data Memory 1 MUX 0 Data B 0 MUX 1 SelB Addr Data Data Rt MUX Rd Sel C LD Instruction Memory Data Data C ALU Adder Adder Offset, Addr, Immediate Sign Extend

  26. Program Setup • Write a Program • Assemble it • Store it in Memory Example: Memory 001101 000000 000100 00000 00001 00001 00001 00001 00001 0000 0000 0000 1010 1111 1111 1111 1111 00001 00000 100000 0 4 8 3 4 0 1 0 0 0 A 0 0 2 1 0 8 2 0 1 0 2 1 F F F F

  27. Datapath Operation CLK PC I-Mem • Fetch Instruction • Decode Instruction • Get Operands • Execute it 0 ƮM Adder MUX PC Adder 0 1 ƮAdder RegASel 2 (Add) 10 0 10 10 4 RegCSel Reg CLD ALU MUX ALU Ctrl Mem MUX Data A ƮReg Sign Ext 3401000A (LDI R1, 10) ALU ƮALU Data C Rs Rt Immediate ƮReg 13 0 1 10

  28. Datapath Operation CLK PC I-Mem • How Fast Can the Clock Be? 0 ƮM Adder MUX Ʈclk PC Adder 0 1 RegASel 4 2 (Add) 10 0 10 10 RegCSel Reg CLD ALU MUX ALU Ctrl Mem MUX Data A ƮReg Sign Ext 3401000A (LDI R1, 10) ALU ƮALU Data C ƮReg

  29. Datapath Operation CLK PC I-Mem • Fetch Instruction • Decode Instruction • Get Operands • Execute it 0 4 Adder MUX PC Adder 4 1 1 RegASel 0 8 2 (Add) 10 10 20 20 RegCSel 1 Reg CLD ALU MUX ALU Ctrl 2 Mem MUX Data A 0 Data B 00210820(Add R1,R1,R1) ALU 10 Data C 10 Rs Rt Rd Shift Funct 0 1 1 1 0 32

  30. Datapath Operation CLK PC I-Mem • Fetch Instruction • Decode Instruction • Get Operands • Execute it 4 8 PC Adder 8 1 1 PC Adder 2 Adder MUX 12 8 6 (Sub) 20 20 0 RegASel 1 RegCSel 1 Reg CLD ALU MUX ALU Ctrl 2 Data A 10 Data B 10 1021FFFF (JE R1,R1,-1) ALU 20 Rs Rt Offset 4 1 1 – 1

  31. Datapath Operation CLK PC I-Mem • How Fast Can the Clock Be? 4 8 ƮM PC Adder 8 1 1 PC Adder 2 Adder MUX 12 8 6 (Sub) 20 20 0 RegASel 1 RegCSel 1 Reg CLD ALU MUX ALU Ctrl 2 Data A 10 ƮReg Data B 10 1021FFFF (JE R1,R1,-1) ALU 20 ƮALU

  32. Datapath Operation CLK PC I-Mem • How Fast Can the Clock Be? 4 8 ƮM PC Adder 8 Ʈclk ƮAdder 1 1 PC Adder 2 ƮAdder Adder MUX 12 8 6 (Sub) 20 20 0 RegASel 1 RegCSel 1 Reg CLD ALU MUX ALU Ctrl 2 Data A 10 ƮReg Data B 10 1021FFFF (JE R1,R1,-1) ALU 20 ƮALU

  33. Single-Cycle Implementation CLK PC I-Mem • Fetch Instruction • Decode Instruction • Get Operands • Execute it i RegASel 3 RegCSel 4 Reg CLD 2 (Add) 7 d d+7 v v ALU MUX ALU Ctrl Mem MUX Data A Sign Ext ALU D-Mem 8C640007(LD R4,[R3+7]) Data C Rs Rt Address 35 3 4 7

  34. Single-Cycle Implementation CLK PC I-Mem • Clock Speed? i ƮM RegASel Ʈclk 3 RegCSel 4 Reg CLD 2 (Add) 7 d d+7 v v ALU MUX ALU Ctrl Mem MUX Data A ƮReg Sign Ext ALU ƮALU D-Mem ƮM 8C640007(LD R4,[R3+7]) Data C ƮReg

  35. Single-Cycle Implementation Example: ƮM= 200 picoseconds ƮALU = 100 picoseconds ƮAdder = 100 picoseconds ƮReg= 50 picoseconds Fastest Clock? Load Immediate/ALU: Ʈclk>ƮM+2ƮReg+ ƮALU Load Memory: Ʈclk>2ƮM+2ƮReg+ ƮALU Store Memory: Ʈclk>2ƮM+ƮReg+ ƮALU Conditional Jump: Ʈclk>Max ƮM+ƮReg+ƮALU 2ƮAdder Ʈclk=ps GHz

  36. Multicycle Implementation • Instructions take different number of clock cycles • Functional units can be shared within the execution of a single instruction Register File SelA Data A X IR Data B SelB PC Memory Result Addr Sel C LD Y MDR Data C ALU Data Data

  37. Multicycle Implementation • Some registers are not visible to the programmer IR X Register File PC Result SelA Data A Y 4 Data B SelB Memory MDR Addr Sel C LD Data C Sign Extend ALU Shift Left 2 Data Data Exercise: Can you do all the previous instruction here?

  38. Multicycle Implementation • Some registers are not visible to the programmer 0 1 2 3 0 1 IR X 0 1 0 1 0 1 0 1 Memory Register File Result PC SelA Data A Y 4 Data B SelB MDR Addr Sel C LD Data Data C Sign Extend ALU Shift Left 2 Data

  39. Multicycle Datapath Operation 1 CLK PC • Fetch Instruction 0 MemRd Ʈclk IRLD IR Mem Out 4 ƮM X MUX Y MUX 0 ALU Ctrl 2 (Add) ALU ƮALU PCMUX PCLD 3401000A

  40. Multicycle Datapath Operation 2 CLK PC • Fetch Instruction • Decode Instruction • Get Operands 0 4 MemRd IRLD 0 IR 3401000A (LDI R1, 10) Mem Out 10 0 Ʈclk RegASel XLD X Data A ƮReg Sign Ext Rs Rt Immediate 13 0 1 10

  41. Multicycle Datapath Operation 3 CLK PC • Fetch Instruction • Decode Instruction • Get Operands • Execute it 4 IR 3401000A (LDI R1, 10) XLD X 0 X MUX 10 Y MUX 2 ALU Ctrl 2 (Add) Ʈclk ResultLD Result ALU ƮALU Rs Rt Immediate 13 0 1 10

  42. Multicycle Datapath Operation 4 CLK PC • Fetch Instruction • Decode Instruction • Get Operands • Execute it 4 IR 3401000A (LDI R1, 10) ResultLD Result 10 RegCSel 1 C MUX Reg CLD Ʈclk ƮReg ƮM Ʈclk>Max ƮALU ƮReg Rs Rt Immediate 13 0 1 10

  43. Multicycle Datapath Operation CLK PCLD PC 0 4 MemRd Mem Out IRLD 3401000A IR 3401000A (LDI R1, 10) RegASel 0 Data A 0 XLD X 0 Sign Ext 10 ALU Ctrl 2 (Add) 2 (Add) ALU 4 10 ResultLD Result 10 RegCSel 1 RegCWrite Rs Rt Immediate IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Rs R  X+IR[15:0] Immediate Reg[IR[20:16]]  R Rt . 13 0 1 10

  44. Multicycle Datapath Operation CLK PCLD PC i i+4 MemRd Mem Out IRLD instruction IR instruction RegASel Rs Selection Data A Rs XLD X Rs Sign Ext value ALU Ctrl Add Add Opcode ALU i+4 i+4+disp result ResultLD Result i+4+disp result RegCSel Rd Rt RegCWrite ALU Operation: R  X op Y R  X op IR[16:0] LD Operation: Reg[IR[20:16]]  MDR. X  Reg[IR[25:21]] Y  Reg[IR[20:16]] R  PC+IR[16:0]] IR  M[PC] PC  PC + 4 Reg[IR[15,11]]  R MDR  Mem[R] Mem[R]  Y

  45. Multicycle Implementation Example: ƮM= 200 picoseconds ƮALU = 100 picoseconds ƮAdder = 100 picoseconds ƮReg= 50 picoseconds Fastest Clock? Load Immediate/ALU: 4 Clocks Load Memory: 5 Clocks Store Memory: 4 Clocks Conditional Jump: 3 Clocks Ʈclk=ps GHz

  46. Control Implementation Datapath Control Signals: ALU Operation, MUX Selection,Memory Rd/Wr, etc Control Unit CU Data Processing Unit DPU or Datapath • • • • • • Datapath Status Signals: IR Fields, ALU Flags

  47. Control Implementation • Hardwired • Standard Logic Components • Fast • Not Flexible, i.e. Difficult to Change Control Operation • Microprogrammed • Memory-Based • Speed Function of Memory (slower than hardwired) • Flexible Design

  48. Control Implementation • Hardwired • FiniteStateMachine Control Unit CombinationalControlLogic Datapath Control Outputs • • • • • • • • • State Register Datapath Control inputs • • •

  49. Microprogrammed Control Implementation • Each Linein the Micro-ProgramExecutesMicro-Operations(in 1 Clock) • Fetch,Decode,ExecuteCycle Control Unit Microprogram Counter Microprogram Memory (Microstore) ALU Operation, MUX Selection,Memory Rd/Wr, etc

  50. Microprogram Control Unit Datapath Control Signals:

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