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Chapter 8

Chapter 8. Sequential Logic Design Practices. Preface. 8.1 Sequential-Circuit Documentation Standards. 1.State-Machine Descriptions. ■ State Table. ■ State Diagram. ■ Transition Lists. 2.Timming Diagram and Specifications. ■ The Cause-and-effect Delays between Critical Signals.

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Chapter 8

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  1. Chapter 8 Sequential Logic Design Practices

  2. Preface

  3. 8.1 Sequential-Circuit Documentation Standards 1.State-Machine Descriptions ■State Table ■State Diagram ■Transition Lists 2.Timming Diagram and Specifications ■The Cause-and-effect Delays between Critical Signals ■A Detailed of Propagation Delays ADE7754 Serial Write Timing

  4. 8.2 Latches and Flip-Flops (SSI Latches and Flip-Flops) Two Independent Positive Edge-Triggered D Flip-Flops with Preset and Clear. 74×74 Two Independent Positive Edge-Triggered Flip-Flops with Preset and Clear. 74×109 Two Independent Negative Edge-Triggered J-K Flip-Flops with Preset and Clear. 74×112 74×375 Four D Latches. Two Latches with a Common C Control. Four Positive Edge-Triggered D Flip-Flops with Invert Output. All Flip-Flops with a Common Clock and Clear. 4bit Register 74×175 Six Positive Edge-Triggered D Flip-Flops with a Common Clock and Clear. No Invert Output. 6bit Register 74×174 Eight Positive Edge-Triggered D Flip-Flops with a Common Clock. No Invert Output. Three-State Output. 8bit Register 74×374 Eight D Latches with a Common C Control. No Invert Output. Three-State Output. 8bit Latch 74×373 Eight Positive Edge-Triggered D Flip-Flops with a Common Clock and Clear. No Invert Output. 8bit Register 74×273 Eight Positive Edge-Triggered D Flip-Flops with a Common Clock and EN. No Invert Output. 8bit Register 74×377

  5. SW_L DSW +5V SW_L DSW SW +5V SW_L S Q R Q Q QL DSW Switch Debouncing

  6. Q Q T Q0 Q1 Q2 Q3 Q Q Q Q Q Q Q Q CLK T T T T 8.3 Counters S2 S1 Modulo-m Counter S3 Divide-by-m Counter Sm S4 S5 T Flip-Flop 1. Ripple Counters Divide-by-2 Counter Asynchronous Counter

  7. CLK Q0 Q1 Q2 Q3 Q0 CLK Q1 Q Q Q Q Q Q Q Q T T T T Q2 Timming Diagram: tpLH tpHL

  8. 2. Synchronous Counters Serial Enable Parallel Enable

  9. CLK Q0 Q0 Q1 Q2 Q2 Serial Enable: If CLK is very fast Pulse be Lose

  10. Synchronous 4-bit Binary Counter 74×163 Input: Clock CLR_L (Synchronous Clear) LD_L (Load) ENP (Enable) ENT (Preset) A,B,C,D (Count Output) Output: QA,QB,QC,QD RCO (Ripple Carry Out)

  11. RCO 0 0 74×163 0 0 0 0 0 0 State Table 0 0 0 0 0 0 0 0 0 1

  12. 74×163 Logic Diagram

  13. Free-Runing Mode Timming Diagram:

  14. Using 74×163 to Design Modulo-M Counter ① Preset Synchronously Counting Seuence Table QD QC QB QA N 0 0 1 0 1 0 1 1 0 1 0 1 1 1 2 1 1 0 0 0 0 3 1 1 0 0 1 4 0 1 0 1 0 5 1 0 1 1 6 1 1 0 0 7 1 1 0 1 8 Modulo-11 Counter 1 1 1 0 9 1 1 1 1 10 RCO=1 LD=0

  15. CLK 1 Counting Sequence Table QD QC QB QA N 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 0 0 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 Modulo-11 Counter 1 0 0 1 9 1 0 1 0 10 QDQB=1 LD=0

  16. Z CLK 1 Using 74×163 to Design Modulo-24 Counter Need Two 74×163s Last State: 00011000 Initial State: 00000001 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0

  17. CLK 1 ② Clear Feedback Counting Sequence Table QD QC QB QA N 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 QDQB=1 CLR=0

  18. CLK 1 0 0 1 ③ Preset More Times Counting Sequence Table QD QC QB QA N Assume 0 0 0 0 0 0 1 0 0 1 0 1 0 1 2 0 1 1 0 3 0 1 1 1 4 1 0 0 0 5 1 1 0 0 6 1 1 0 1 7 1 1 1 0 8 1 1 1 1 9 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1

  19. 74×161 Up/Down Counter No Clear ENP ENT Low Active RCO Low Active Same Pinout as 74×163 Asynchronous Clear Input

  20. Decoding Binary-Counter States

  21. Decoder with Glitch-Free Output Homework:8.13,8.42,8.46

  22. 8.4 Shift Registers Serial-In, Serial-Out Serial-In, Parallel-Out

  23. 1Q 2Q NQ Serial-In, Serial-Out Serial-In, Parallel-Out Parallel-In, Serial-Out Parallel-In, Parallel-Out

  24. MSI Shift Registers Universal Serial-In, Parallel-Out Parallel-In, Serial-Out

  25. Parallel/Serial Conversion 1 1 1 0

  26. Serial/Parallel Conversion 0 0 0 0

  27. Ring Counters Counting Sequence Table QD QC QB QA LIN 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 Single circulating 1 0000 0000 1111 1000 1111 0111 0100 0001 0011 1011 1110 0010 1001 0110 1101 0101 1010 1100

  28. Counting Sequence Table QD QC QB QA LIN Four States FeedbackEquation 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 Single circulating 1 Self-Correcting

  29. State Diagram 1101 1100 0000 1000 0110 0100 1111 0001 0011 0010 1001 0111 0101 1110 1010 1011

  30. Counting Sequence Table QD QC QB QA LIN Four States FeedbackEquation 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 1 Single circulating 0 Self-Correcting

  31. Johnson Counters Counting Sequence Table QD QC QB QA LIN 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 Eight States 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 Eight States 1 0 1 0 1 FeedbackEquation 1 1 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0

  32. Counting Sequence Table QD QC QB QA LIN S0 0 0 0 0 1 0 d 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 Eight States 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 Self-Correcting 1 0 0 1 0 d 0 1 0 0 1 d 00 01 11 10 1 0 1 0 1 d 00 d d 0 0 1 1 0 1 0 d 01 0 1 1 0 1 d 0 d d d 1 0 1 1 0 d 11 0 0 0 d 0 1 0 1 0 d 10 d 1 0 d

  33. (LFSR) Linear Feedback Shift-Register Counters Finite Fields Theory Ex.8-1 Modulo-7 System U=(0,1,2,3,4,5,6) Original Element:2 4+2=6 6+2=8 1 1+2=3 3+2=5 2+2=4 0+2=2 5+2=7 0 n-bit Shift-Register has 2n-1 Nonzero States! Maximum-Length Sequence Producing Random Numbers

  34. X2 X1 X0 X3(LIN) 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 0 Seven Nonzero States 0 0 1 1 0 0 0 0 X2 X1 X0 Not Self-Correcting

  35. X2 X1 X0 X3(LIN) X2 X1 X0 X3(LIN) 1 0 0 1 00 01 11 10 1 0 0 0 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 1 1 1 00 01 11 10 1 1 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 Homework:8.55

  36. 8.5 Iterative versus Sequential Circuits Serial Comparator Serial adder

  37. 8.6 Sequence Generator 0 CLK 1 Counter + Combinational Logic Maximum-Length Sequence Generator Ex.8-2 Produce 110001001110 Sequence ①Modulo-12 Counter + Combinational Logic Using Counter QD QC QB QA F 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 F 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 d

  38. Using Shift Register 00 01 11 10 00 0 d 0 d QA QB QC QD LIN S0 F 01 0 0 d 0 S0 0 0 0 0 1 0 1 11 0 0 0 0 0 0 0 1 1 0 1 10 1 0 0 d 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 0 00 01 11 10 00 01 11 10 1 0 0 1 0 0 0 00 1 d 1 d 00 0 0 1 0 1 0 1 1 d 0 d 01 1 1 d 0 0 1 0 1 1 0 1 01 LIN 1 1 d 0 F 11 1 0 1 1 1 0 0 1 1 0 0 11 0 0 0 1 0 1 1 0 1 1 0 10 0 1 1 d 10 1 1 0 d 1 1 0 1 d d d

  39. CLK 0 1 0 0 0 0 F 1 1 0 0 1 0 0100 1001 States Check Self-Correcting 1000 0001 1001 1010 0100 1001 1101 1010 0100

  40. CLK 1 0 0 ②Maximum-Length Sequence Generator LIN(F) QA QB QC QD 1 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 F 0 1 0 0 1 F4 1 1 1 1 0 0 F3 0 0 1 1 1 0 F2 0 0 0 1 1 1 F1 1 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 0 0 00 0 01 11 10 0 0 1 1 00 d 0 1 1 01 1 d 1 1 0 0000 0001 0101 1011 F States Check 1111 1110 11 1011 0 1010 0101 0 d 1 0101 1010 Self-Correcting 10 0 0 1 d 1010 0101

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