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CS1104: Computer Organisation comp.nus.sg/~cs1104

CS1104: Computer Organisation http://www.comp.nus.edu.sg/~cs1104. School of Computing National University of Singapore. PII Lecture 5: Basic MIPS Assembly Language. Basic MIPS R2000 ISA MIPS Assembly Language Arithmetic operations Load/store instructions for memory data Control flow

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CS1104: Computer Organisation comp.nus.sg/~cs1104

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  1. CS1104: Computer Organisation http://www.comp.nus.edu.sg/~cs1104 School of Computing National University of Singapore

  2. PII Lecture 5: Basic MIPS Assembly Language • Basic MIPS R2000 ISA • MIPS Assembly Language • Arithmetic operations • Load/store instructions for memory data • Control flow • Constant handling • Branch addressing Basic MIPS Assembly Language

  3. PII Lecture 5: Basic MIPS Assembly Language • Reading: Chapter 3 of Patterson’s book: • 3.1 – 3.5, 3.8, 3.11, 3.13, 3.14. • Optional reading: 3:10, 3.12. • PCSpim (MIPS R2000 simulator) • ftp://ftp.cs.wisc.edu/pub/spim/pcspim.exe or • http://www.cs.wisc.edu/~larus/spim.html Basic MIPS Assembly Language

  4. MIPS R2000 ISA Basic MIPS Assembly Language

  5. MIPS R2000 ISA • The MIPS instruction set is typical of RISC (Reduced Instruction Set Computers) architectures (MIPS, PowerPC, SPACRC, ARM, etc.) • MIPS R2000 is a load-store register architecture. • MIPS R2000 Assembly Language: • 32 registers, each 32-bit (4-byte) long. • Each word contains 32 bits (4 bytes). • Memory addresses are 32-bit long. Basic MIPS Assembly Language

  6. MIPS Operands: Registers and Memory MIPS operands Basic MIPS Assembly Language

  7. MIPS Operands: Registers and Memory (2) $at (register 1) is reserved for the assembler. $k0-$k1 (registers 26-27) are reserved for the operation system. Basic MIPS Assembly Language

  8. MIPS: Addressing Modes • Mainly 5 types of addressing modes: • Register • Immediate • Displacement (with a base register and a constant) • PC-relative • Pseudo-direct (with 26 bits concatenated with PC upper bits for jump address) • Computation instructions operate only on values in registers or immediate values embedded in the instructions. • Data in memory can be accessed through one memory addressing mode, C(Rx), where C is an immediate constant and Rx is a register. Basic MIPS Assembly Language

  9. op rs rt rd register op rs rt immed Memory op rs rt immed register + + Memory op rs rt immed PC MIPS: Addressing Modes (2) Register (direct) Immediate Displacement PC-relative Basic MIPS Assembly Language

  10. 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-format op rs rt rd shamt funct I-format op rs rt 16-bit immed/address J-format op 26-bit address MIPS: Instruction Format • Fixed-length instruction format. • All instructions are 32-bit long. • Very structured. • Only three instruction formats: R, I, J. Basic MIPS Assembly Language

  11. 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000 MIPS: Instruction Format (2) • R-format: Used for instructions with 3 register operands. • Arithmetic instructions: add $t0, $s1, $s2 # $t0  $s1 + $s2 Recall that $t0 is register 8, $s1 is register 17 and $s2 is register 18. R-format Basic MIPS Assembly Language

  12. op rs rt 16-bit immed/address 100011 10010 01000 0000000000101000 6 bits 5 bits 5 bits 16 bits MIPS: Instruction Format (3) • I-format: For data transfer instructions. • Examples: load word (lw) and store word (sw). • One register operand and one memory address operand (specified by a constant and a register) lw $t0, 40($s2) # load Mem[$s2+40] to $t0 Recall that $t0 is register 8 and $s2 is register 18. I-format Basic MIPS Assembly Language

  13. MIPS: Opcodes • Learn by examples. • Focus mainly on those simple ones, such as: load store add subtract move register-register and shift compare equal, compare not equal branch jump call return Basic MIPS Assembly Language

  14. Basic MIPS Assembly Language Basic MIPS Assembly Language

  15. Assembly vs. Machine Language • Assembly provides convenient symbolic representation. • Much easier than writing down binary numbers (“add” instead of 000000). • Destination first. • Example: Add A, B, C # A  B + C • Machine language is the underlying reality • Destination needs not be specified first. • Example: op rs rt rd • Assembly can provide pseudo-instructions • Example: “move $t0, $t1” exists only in assembly, implemented using “add $t0, $t1, $zero”. • When considering performance, count real instructions. Basic MIPS Assembly Language

  16. Arithmetic Instructions • All instructions have 3 operands. • Operand order is fixed. • Example: • C code: A = B + C; • MIPS code: add $s0, $s1, $s2 • Compiler associates registers with variables in program. Basic MIPS Assembly Language

  17. Arithmetic Instructions (2) • Design principle: simplicity favours regularity. • This complicates some things… • C code: Variable number of operands A = B + C + D; E = F – A; • MIPS code: add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0 • MIPS operands must be registers. Basic MIPS Assembly Language

  18. Load/Store Instructions • Only load and store instructions can access memory data. • Example: Each array element occupies a word. • C code: A[7] = h + A[10]; • MIPS code: lw $t0, 40($s3) add $t0, $s2, $t0 sw $t0, 28($s3) • Each array element occupies a word (4 bytes). • $s3 contains the base address (address of first element) of array A. • Remember arithmetic operands (for add) are registers, not memory! Basic MIPS Assembly Language

  19. Load/Store Instructions (2) • Besides the load word (lw) and store word (sw) instructions, there are also the load byte (lb) and store byte (sb) instructions. • Similar in format: lb $t1, 12($s3) sb $t2, 13($s3) • Similar in working except that one byte, instead of one word, is loaded or stored. Basic MIPS Assembly Language

  20. Load/Store Instructions (3) • MIPS disallows loading/storing a word that crosses the word boundary. Use the unaligned load word (ulw) and unaligned store word (usw) instructions instead. These are pseudo-instructions. • There are other instructions such as • lh and sh: load halfword and store halfword • lwl, lwr, swl, swr: load word left, load word right, store word left, store word right. • And others. Basic MIPS Assembly Language

  21. $5 contains k. $2 contains 4*k (because each word contains 4 bytes) Base address of array v in $4 First Example • Figure out the code. swap(int v[], int k) { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 Basic MIPS Assembly Language

  22. Conditional Control • Decision making instructions • Alter the control flow. • Changing the next instruction to be executed. • MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label • Example: if (i == j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label: … Basic MIPS Assembly Language

  23. Unconditional Control • MIPS unconditional branch instruction: j (jump) j Label • Example: if (i != j)beq $s4, $s5, L1 h = i + j; add $s3, $s4, $s5 else j L2 h = i – j; L1: sub $s3, $s4, $s5 L2: … • Can you write the MIPS code for a simple for loop? Basic MIPS Assembly Language

  24. 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-format op rs rt rd shamt funct I-format op rs rt 16-bit immed/address J-format op 26-bit address So far we’ve learned: • Arithmetic on registers only • Loading/storing words but addressing bytes. Instruction Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 – $s3 lw $s1, 100($s2) $s1 = Mem[$s2+100] sw $s1, 100($s2) Mem[$s2+100] = $s1 bne $s1, $s2, L next instr. at L if $s1 ≠ $s2 beq $s1, $s2, L next instr. at L if $s1 = $s2 j L next instr. at L Basic MIPS Assembly Language

  25. More About Control Flow • We have beq and bne, what about branch-if-less-than? We do not have a blt instruction. • Use slt (set on less than). if $s1 < $s2 then $t0 = 1 else $t0 = 0 slt $t0, $s1, $s2 = • To build a “blt $s1, $s2, Label” instruction: slt $t0, $s1, $s2 bne $zero, $t0, Label • We can now build general control structures. Basic MIPS Assembly Language

  26. Constants • Small constants are used quite frequently (50% of operands). A = A + 5; B = B + 1; C = C – 18; • Solution: • Put ‘typical constants’ in memory and load them. • Create hard-wired registers (like $zero) for constants like one. • Embed them into the instruction code. • For MIPS instructions, we use the ‘immediate operand’ version: addi $29, $29, 4 slti $8, $18, 10 andi $29, $29, 6 ori $29, $29, 4 Basic MIPS Assembly Language

  27. 1010 or 1001  1011 1010 1001 or 1011 Larger Constants • Bit-wise operations: or, ori, and, andi. • Examples: 1010 and 1001  1000 1010 1001 and 1000 Basic MIPS Assembly Language

  28. Lower-order bits filled with zeros. 1010101010101010 0000000000000000 1010101010101010 1010101010101010 0000000000000000 1111000011110000 0000000000000000 1111000011110000 ori Larger Constants (2) • How to load a 32-bit constant into a register. • Example: 1010101010101010 1111000011110000? • Need to use two instructions: “load upper immediate” (lui) and “or immediate” (ori): lui $t0, 1010101010101010 • Then to get the lower-order bits correct: ori $t0, $t0, 1111000011110000 Basic MIPS Assembly Language

  29. Larger Constants (3) • The above are just illustration of the concept. In the actual instruction, the value is entered as a decimal value or an hexadecimal value (prefixed by 0x). • For example lui $t0, 43690 # 4369010 = 10101010101010102 or lui $t0, 0xAAAA # AAAA16 = 10101010101010102 Basic MIPS Assembly Language

  30. I-format op rs rt 16-bit immed/address J-format op 26-bit address Addresses in Branches and Jumps • Instructions: bne $t1, $t2, Label # next instr. at Label if $t1 ≠ $t2 beq $t1, $t2, Label # next instr. at Label if $t1 = $t2 j Label # next instr. at Label • Formats: • How is the branch address formed? • How does this differ from the address calculation in Load/Store instructions? Basic MIPS Assembly Language

  31. I-format op rs rt 16-bit immed/address Addresses in Conditional Branches • Examples: bne $t1, $t2, Label # next instr. at Label if $t1 ≠ $t2 beq $t1, $t2, Label # next instr. at Label if $t1 = $t2 • Formats: • Specify a register (like lw and sw) and add it to the specified address • Use Instruction Address Register, or PC (program counter) • Most branches are local (principle of locality) • Address = PC + shift_left_2_bits(16-bit address) • Why do we shift the specified 16-bit address by 2 bits to the left? Basic MIPS Assembly Language

  32. J-format op 26-bit address Addresses in Unconditional Jumps • Example: j Label # next instr. at Label • Formats: • Jump instructions just use high-order bits of PC • Address = bits 31-28 of PC + shift_left_2_bits(26-bit address) • Address boundaries of 256 MB. Basic MIPS Assembly Language

  33. MIPS Instructions: Summary Basic MIPS Assembly Language

  34. Initialization for result variables, loop counter, and array pointers. • Work by: • Calculating address • Load data • Perform task Label: Update loop counter and array pointers. Compare and branch. Array and Loop • Typical example of accessing array elements in a loop: Basic MIPS Assembly Language

  35. Array and Loop: Example • Given a word array A with 40 elements A[0], A[1], …, A[39], with the starting array address stored in $t0. Count the number of array elements with value zero, and store the result in $t8. Answer 1: addi $t8, $zero, 0 /* initialize counter to zero addi $t1, $zero, 0 /* $t1 as index ptr, init. to pt. 1st element L1: add $t2, $t0, $t1 /* address of current element lw $t3, 0($t2) /* load current element from memory bne $zero, $t3, L2 /* check if data is zero, if not, skip update addi $t8, $t8, 1 /* increment counter L2: addi $t1, $t1, 4 /* point to next element (How to compare and loop back?) bne $t1, 160, L1 ??? No immediate compare operand! Basic MIPS Assembly Language

  36. Array and Loop: Example (cont’d) Answer 2: addi $t8, $zero, 0 /* initialize counter to zero addi $t1, $zero, 156 /* $t1 as index ptr, init. to pt. last element L1: add $t2, $t0, $t1 /* address of current element lw $t3, 0($t2) /* load current element from memory bne $zero, $t3, L2 /* check if data is zero, if not, skip update addi $t8, $t8, 1 /* increment counter L2: addi $t1, $t1, –4 /* point to previous element bne $t1, $zero, L1 (How about the iteration for the first element?) Basic MIPS Assembly Language

  37. Array and Loop: Example (cont’d) Answer 3: addi $t8, $zero, 0 /* initialize counter to zero addi $t1, $zero, 160 /* $t1 as index ptr, init. to pt. pass /* last element L1: add $t2, $t0, $t1 /* address of current element lw $t3, –4($t2) /* load preceding element from memory bne $zero, $t3, L2 /* check if data is zero, if not, skip update addi $t8, $t8, 1 /* increment counter L2: addi $t1, $t1, –4 /* point to previous element bne $t1, $zero, L1 (Is this correct now?) Basic MIPS Assembly Language

  38. Other Issues • Things we are not going to cover: • Support for procedures • Linkers, loaders, memory layout • Stacks, frames, recursion • Manipulating strings and pointers • Interrupts and exceptions • System calls and conventions Basic MIPS Assembly Language

  39. Concepts of Focus • Basic MIPS ISA • Basic assembly language programming • Arithmetic: among registers only • Memory accesses: load/store only • Control flow: for loop, if-then-else. • Handling of constants and branch address data. • Practice is the key to master the techniques • Memorization will not help you! Basic MIPS Assembly Language

  40. MIPS R2000 Simulator • Try out PCSpim (MIPS R2000 simulator) • ftp://ftp.cs.wisc.edu/pub/spim/pcspim.exe or • http://www.cs.wisc.edu/~larus/spim.html Basic MIPS Assembly Language

  41. Sample Question (1) • Which of the following statements is/are true? • In MIPS architecture, the smallest unit of memory to have an unique memory address is a word. • Big and little endians refer to the two dimensions of the array data stored in memory. • Mis-alignment of data along non-word boundary will suffer performance loss, but not the program accuracy. • (a) and (c). • None of the above. [Answer] Basic MIPS Assembly Language

  42. Sample Question (2) • Which of the following data can be a valid operand for a MIPS arithmetic instruction? Assume that $t4 is a register in MIPS. • 4000000000 • 64($t4) • $t4(0) • (b) and (c) • None of the above. [Answer] Basic MIPS Assembly Language

  43. Sample Question (3) • Which of the following is true for the MIPS instruction format? • Conditional branch instructions can be in J-format. • MIPS has variable-length instruction format. • All MIPS arithmetic instructions are in R-format only. • lw/sw instructions are in I-format only. • None of the above. [Answer] Basic MIPS Assembly Language

  44. Sample Question (4) • Which of the following data can be a valid destination operand for a MIPS lw instruction? Assume that $s0 is a register in MIPS. • $s0(32) • 100 • 100000000 • 32($s0) • None of the above. [Answer] Basic MIPS Assembly Language

  45. Sample Question (5) • In the MIPS architecture, which of the following is false for the data in memory? • Data in memory can be viewed as a single-dimension array, with the memory address as an index into the array. • Data in memory is byte-addressing (i.e. each byte has an unique memory address). • Data in memory is always aligned with the word boundary. • Data in memory can be accessed directly by a subset of the MIPS instructions only. • None of the above. [Answer] Basic MIPS Assembly Language

  46. Sample Question (6) • Under the addressing modes of the MIPS architecture, which of the following is true? • There is no data memory READ for an operand under the “immediate” addressing mode. • Two instructions are always required to load 32-bit data from the memory into a register: “lui” to load the upper 16 bits and then “ori” to put the lower 16 bits into the register. • The “register” addressing mode can be used to load a datum from the memory into a register. • The “displacement” addressing mode can be used to specify an operand in a MIPS arithmetic instruction. • None of the above. [Answer] Basic MIPS Assembly Language

  47. Sample Question (7) • Given a word array of data A[0], A[1], A[2], …, A[10] in memory, with the starting address stored in register $t4, element A[6] can be loaded into a register $t5 using the following instruction: • lw $t5, A[6] • lw $t5, $t4[6] • lw $t5, 6($t4) • lw $t5, $t4[24] • None of the above. [Answer] Basic MIPS Assembly Language

  48. Sample Question (8) • Which of the following data is/are valid source operand(s) for the MIPS lw instruction? • 100 • $s0 • 32($s2) • (a) and (c) • None of the above. [Answer] Basic MIPS Assembly Language

  49. Sample Question (9) • Which of the following data is not a valid basic MIPS instruction? • add $t0, $zero, $zero • addi $t0, $t0, –1 • lw $t0, 8096($t1) • beqi $t0, 4, label • None of the above. [Answer] Basic MIPS Assembly Language

  50. Sample Question (10) • Given the following MIPS instruction sequence: addi $t1, $zero, 10 add $t1, $t1, $t1 addi $t2, $zero, 10 Loop1: addi $t2, $t2, 10 subi $t1, $t1, 1 beq $t1, $zero, Loop1 • How many instructions are executed? (a) 6 (b) 30 (c) 33 (d) 36 (e) None of the above • What is the final value in $t2? (a) 10 (b) 20 (c) 300 (d) 310 (e) None of the above [Ans] [Ans] Basic MIPS Assembly Language

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