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Lecture 6: Assembly Language

Lecture 6: Assembly Language. Computer Engineering 211 Spring 2002. i $r1 AddrA  $r2 A[i]  $r4. While Loops. i=0; while (A[i]!=0) { A[i] = A[i] + 5; i=i+1; }. Version 1 move $r1, $r0 #i=0 Loop: add $r3, $r1, $r2 # $r3  Addr[A[i]]

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Lecture 6: Assembly Language

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  1. Lecture 6: Assembly Language Computer Engineering 211 Spring 2002

  2. i $r1 AddrA  $r2 A[i]  $r4 While Loops i=0; while (A[i]!=0) { A[i] = A[i] + 5; i=i+1; } Version 1 move $r1, $r0 #i=0 Loop: add $r3, $r1, $r2 # $r3  Addr[A[i]] lw $r4, 0($r3) #$r4  A[i] beq $r4, $r0, Exit addi $r4, $r4, 5 # A[i]  A[i]+5 sw $r4, 0($r3) # write A[i] addi $r1, $r1, 4 #i  i+1 j Loop Instructions:1+7*N +3 Registers:4

  3. Version 2 move $r1, $r0 #i=0 add $r3, $r1, $r2 # $r3  Addr[A[i]] lw $r4, 0($r3) #$r4  A[i] beq $r4, $r0, Exit Loop: addi $r4, $r4, 5 # A[i]  A[i]+5 sw $r4, 0($r3) # write A[i] addi $r1, $r1, 4 #i  i+1 add $r3, $r1, $r2 lw $r4, 0($r3) bne $r4, $r0, Loop Exit: While Loops Contd. Instructions:4+6*N Registers:4

  4. Machine Level Instructions • Machine only understands binary instructions. • For controller’s efficiency: all instructions of same length (32-bits). • An instruction has distinct fields: opcode, destination, src op1, src op2. • Each field in the same place for all (most) instructions – uniform encoding.

  5. Arithmetic instruction: 5-bits 5-bits 5-bits 5-bits 6-bits 6-bits opcode src1 src2 dest function add $r8, $r20, $r24 0 20 24 8 0 32 000000 10100 11000 01000 00000 100000 Instruction Encoding

  6. sub $r2, $r2, $r1 000000 0 0 000000 2 00010 2 00010 3 00001 00011 1 1 2 00010 00001 00000 0 0 00000 100010 0x2a 34 101010 slt $r1, $r2, $r3 Instruction Encoding Contd. R-Format instruction

  7. addi $r2, $r1, -1 16-bits immediate 8 1 2 -1 001000 00001 00010 1111 1111 1111 1111 slti $r1, $r2, 1025 0xa 2 1 1025 001010 00010 00001 0000 0100 0000 0001 Instruction Encoding Contd. I-Format Instructions

  8. 0x23 2 1 -1 10 0011 00010 00001 1111 1111 1111 1111 Load/Store Encoding R-format; I-format; or a new format? lw $r1, -1($r2) opcode, dest reg, displacement, base reg. 6-bits, 5-bits, 16-bits, 5-bits

  9. lui $r1, 10 0xf 0 1 10 00 1111 00000 00001 0000 0000 0000 1010 Load/Store Encoding Contd. I-format encoding for all loads/stores

  10. Branch instruction encoding beq $r1, $r2, target opcode, src1, src2, target 6-bits, 5-bits, 5-bits, ?? (16-bits left-over) Specify an absolute address in 16-bits? Think displacement! Base register  address of the current (branch) instruction (PC) Displacement  distance between the branch & its target

  11. 1000 1004 1008 1012 1016 1020 1020 Program counter (PC) Branch instruction encoding Loop: lw $r4, 0($r2) addi $r4, $r4, 5 sw $r4, 0($r2) addi $r2, $r2, 4 sub $r6, $r3, $r2 bne $r6, $r0, Loop Distance/target offset between bne & lw? -20 Target = PC + target offset = 1020 + (-20) = 1000

  12. 5 6 0 -20 00 0101 00110 00000 1111 1111 1110 1100 Branch Instruction Encoding contd. bne $r6, $r0, Loop:-20

  13. 5 6 0 -5 bne $r6, $r0, Loop:-5 Branch Instruction Encoding contd. Given that the instructions are 4 bytes wide, are the branch offsets multiples of 4? Branch offset = #instructions * 4 bytes Branch offset values always end in 00. 0: 00000 4: 00100 8: 01000 12: 01100 16: 10000 20: 10100 24: 11000 28: 11100

  14. How is the branch target computed? 5 6 0 1111 1111 1111 1011 1111 1111 1111 1011 = 00 PC PC + Branch offset 2’ comp (5): 5: 00101 1’s comp(5): 11010 +1= 11011 Guess: 1101100 -20? 2’ comp (20): 20: 0010100 1’s comp(20): 1101011 +1= 1101100 Advantage: PC ± 217

  15. j target Opcode: 6 bits; target: 26 bits? Observation: All instruction addresses end in 00. Only 4 bits missing for absolute address specification. Jump instruction encoding bne $r1, $r2, elsepart ifbody j join elsepart: elsebody join: We could make jump target PC-relative. beq $r0, $r0, target already does that.

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