ECEN 248 Lab 8: 16-Bit ALU with 8 operations

1. ECEN 248Lab 8: 16-Bit ALU with 8 operations Dept. of Electrical and Computer Engineering

2. Lab 8 in Brief • Design a 2 operand 16-bit ALU • All operations are signed Operation • Declare all reg, wires, input and output as signed in Verilog • Example: reg signed [15:0] data;

3. ALU Operation Selection codes • Use Case Statement for Operation Selection

4. File Organization • rot_intfc.v (From lab # 7 – Slight Modification) • alu_lcd.v (Submodules: lcd_disp.v, hex_dec.v) • counter.v (Submodules: rot_switch1.v, push_butt.v, sr.v from Lab # 5) • ALU.v Modules that you don’t need to modify: lcd_disp.v, hex_dec.v, counter.v, rot_switch1.v, push_butt.v, sr.v Modules you need to modify are: • alu_lcd: Modify adder_lcd from lab # 5 to accommodate for the ALU display configuration • rot_intfc: Modify rot_intfc.v so that it takes in two 16 bit input and gives out a 32 bit output. Also u need to take in input from switches for selecting operation. • alu.ucf

5. LCD Display Configuration Note: You can use case statements in the adder_lcd file to display the operation as shown in the Selected Operation Section Above

6. ALU Operation Selection codes • Use Case Statement in alu_lcd.v module to set the “Selected Operation” Display

7. Deadlines • Today • Work on Lab 8 • 2 Weeks later • Lab 8 Post-Lab due • Lab 9 Pre-Lab due at the beginning of class