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Heterogeneous Chip Multiprocessor Design for Virtual Machines. Dan Upton and Kim Hazelwood University of Virginia. Pairing CMPs and VMs. Challenge for chip multiprocessors: exploiting all available thread-level parallelism Challenge for virtual machines: reducing overhead
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Heterogeneous Chip Multiprocessor Design for Virtual Machines Dan Upton and Kim Hazelwood University of Virginia
Pairing CMPs and VMs • Challenge for chip multiprocessors: exploiting all available thread-level parallelism • Challenge for virtual machines: reducing overhead • Our solution: moving the VM to a separate core – only give a VM core what the VM needs
Heterogeneous Chip Multiprocessors • Applications have different needs • Ex: Cache performance, available ILP • Heterogeneous CMPs can be used to meet design constraints • Ex: Size, power, cost
Virtual machines • Many practical applications • Dynamic translation (legacy ISA support) • Security • Instrumentation • … App App App App VM OS OS VM HW HW Process VMs (Ex: Pin, JVM, Rosetta) System VMs (Ex: Xen, Transmeta)
Design Approach • Characterize a VM’s microarchitectural performance • Examine processor organization options • Consider beneficial modifcations for support Application Pin SimpleScalar-x86
Two Examples • Comparison of branch behavior against benchmarks from SPECINT 2000 • Comparison of cache performance • Other experiments in paper
Design Options • Two basic classes: VM General Purpose General Purpose 1 General Purpose 2 General Purpose VM (other specialized) VM VM General Purpose General Purpose VM
Support Structures • Support for tasks normally handled in software where to compile VM Core Application Core support for indirect branches where to resume executing
Related Work • Hardware support for VMs (Trident, DAISY, Kim and Smith) • Transmeta • Java in hardware (picoJava, JOP)
Work in Progress • Comparing similarity of Pin to other VM software • Characterizing VM compilation, cache management