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Programmable System Level Integration

on your desktop. Programmable System Level Integration. Atmel’s North America Logic Seminar Series. San Jose, CA (1,200 employees ) Headquarters, Test and Qualification, R / D Colorado Springs, CO (1,900 employees) Fabrication Assembly & Test, R / D Two 0.35  6 inch Wafer Fabs

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Programmable System Level Integration

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  1. on your desktop Programmable System Level Integration Atmel’s North America Logic Seminar Series

  2. San Jose, CA (1,200 employees) Headquarters, Test and Qualification, R / D Colorado Springs, CO (1,900 employees) Fabrication Assembly & Test, R / D Two 0.35 6 inch Wafer Fabs Rousset, France (600 employees) Fabrication Assembly & Test, R / D 0.5 6 inch Wafer Fab and 0.35 8 inch Wafer Fab Temic: Heilbronn, Germany (900 Employees) 0.5 6 inch Bipolar / Si-Ge Wafer Fab, Assembly, Test, R / D Temic: Nantes, France (650 employees) 0.5 6 inch Wafer Fab, Assembly, Test, R / D ASIC / ASSP Design Centers Columbia, MD; Colo. Spgs.; San Jose; Paris; Munich; Camberley UK; Tokyo; Shanghai; Raleigh, NC; Berkeley, CA; Helsinki; Trondheim All Facilities Registered ISO 9001 & 9002 7 North American & 15 International Sales Offices Facilities and Employees Total 6,100 Employees

  3. Trondheim Helsinki E. Killbride Minneapolis Paris Camberley Dijon Nantes Heilbronn San Jose Tokyo Chesapeake Portugal Rousset Colo Spgs Raleigh Shanghai Greece Hong Kong Malaysia Atmel Product Design Centers IP Expertise NVM, 8, 16, 32-bit MCUs, DSP Core, Analog, RF, Rotating Storage, RFID, Data Security Wireless Voice/Data, Image/Sound Processing, Power Measurement, Battery Management, Automotive, Smart Card, TV/Radio, USB, Wired/Wireless L A N, I R D A, Bluetooth

  4. Cell based ASIC User-Defined Logic Spectrum Custom ASIC Gate Array FPSLIC Density FPGA CPLD PAL- Type Macrocells 0.25, 0.35, 0.5, 0.6 Analog / Digital ATL25 Series ATL35 Series ATL50 Series ATL60 Series ATV2500B ATF1500 Fam ATV750B Analog / Digital/ NV Memory, RF ATF22V10 ATF16V8 ATF20V8 AT6000 AT40K AT94K RAM/Logic, Computing, Co-processing Programmable SLI with AVR Decoders, Glue Logic State machines, Timing, Control Total Customization Very High Volume High Volume/Low Cost System Level Integration

  5. Engine Control Internet Settop Boxes Disk Drives Cellphones Auto Elect. Appliances Keyless Entry Atmel’s Flash MCU FamiliesPrice vs Performance Performance Laser Printer ARM-7 AVR C51 Price $1 $2 $5 $10 $20

  6. SLI Products ASIC • FPGA • Gate Array/Embedded Array • Cell Based IC • Custom ASSP • Multimedia • Storage Products • Smart Cards • Wireless Communications • Wireline Communications • Power MCU Microcontrollers • 80C51 • AVR™ • ARM™

  7. ASSP Multimedia • Sound; Dolby AC3,Voice Recorder andDigital Answering Machine • Image Processing; MPEG2and Video Conferencing • Image Capture WirelessCommunications • Cellular; GSM and CDMA (Baseband) • Networking; Wireless LAN and Bluetooth • RFID; Asset ID and Remote Keyless Entry Wireline Communications • USB; Function, Hostand Hub • Ethernet; 10T/100 MAC and PHY • Cable Modem; QPSKand QAM Power MCU • Power Meters • Battery Chargers Smart Cards • Secure Memories • Secure Microcontrollers Storage Products • DVD/CD-ROM • Floppy Disk • Hard Disk

  8. 0.6µ CMOS in Production 0.5µ CMOS in Production 0.35µ CMOS in Production 0.25µ CMOS in Production 0.18µ CMOS in Development 0.8µ BiCMOS in Production 0.6µ BiCMOS in Development 0.8µ Si-Ge in Production 0.35µ Si-Ge BiCMOS in Development Fab Processes

  9. Clock NVM CPU ASSP Logic Analogue Memory SRAM FPGA Glue Logic Power Management System-On-Chip Issues • $250K+ NRE • $100K+ design tools • Large volume requirements • Custom product • Long design time • High risk • IP issues (availability, cost • implementation) >> System level integration not viable for most customers

  10. 20 MIPS* - 8bit RISC MCU Up to 36K bytes of SRAM Configurable SRAM AT40K FPGA 8 Bit RISC MCU From 5K Up to 40K gates FPGA Monolithic SRAM Based FPSLIC *30 MIPS version available Q4 2001

  11. Configurable SRAM SRAM interface AT40K FPGA 8 Bit RISC MCU AVR/AT40K interface FPSLIC Embedded Blocks • Software configurable interface between blocks already implemented • Pre-implemented Interface blocks save 2000-5000 FPGA gates

  12. AT40K FPGA FPGA Designs Figaro IDS FPGA Development Tools AT17 • IDS supports Schematic, VHDL or Verilog Design Entry • It generates a BST file for programming the Configurator

  13. 8 Bit RISC MCU AVR Designs AVR Studio Instruction Set Simulator Requires an Assembly or C Compiler • AVR Studio can be used with Assembly or C to debug code • A HEX file is then used to program the AVR

  14. FPSLIC Designs System Designer for FPSLIC designs includes FPGA and AVR design flows with Co-verification Configurable SRAM AT40K FPGA 8 Bit RISC MCU

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