Chapter 8: Main Memory

1. Chapter 8: Main Memory

2. Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium

3. Objectives To provide a detailed description of various ways of organizing memory hardware To discuss various memory-management techniques, including paging and segmentation To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging

4. Background A program must be brought (from disk) into memory and placed within a process for it to be run Main memory and registers are the only storage CPU can access directly Register access is in one CPU clock (or less) Main memory can take many cycles Cachesits between main memory and CPU registers Protection of memory required to ensure correct operation

5. Base and Limit Registers A pair of baseandlimitregisters define the logical address space

6. Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses can happen at three different stages Compile time: If memory location known a priori, absolute codecan be generated; must recompile code if starting location changes Load time: Must generate relocatable code if memory location is not known at compile time Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limitregisters)

7. Multistep Processing of a User Program

8. Logical vs. Physical Address Space The concept of a logical address space that is bound to a separate physical address spaceis central to proper memory management Logical address– generated by the CPU; also referred to as virtual address Physical address– address seen by the memory unit Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme

9. Memory-Management Unit (MMU) Hardware device that maps virtual to physical address In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory The user program deals with logical addresses; it never sees the real physical addresses

10. Dynamic Relocation Using a Relocation Register

11. Dynamic Loading Routine is not loaded until it is called Better memory-space utilization; unused routine is never loaded Useful when large amounts of code are needed to handle infrequently occurring cases No special support from the operating system is required - implemented through program design

12. Dynamic Linking Linking postponed until execution time Small piece of code, stub, used to locate the appropriate memory-resident library routine Stub replaces itself with the address of the routine, and executes the routine Operating system needed to check if routine is in processes’ memory address Dynamic linking is particularly useful for libraries System also known as shared libraries

13. Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium

14. Swapping A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution Backing store– fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images Roll out, roll in– swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed

15. Swapping • Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped • Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows) • System maintains a ready queueof ready-to-run processes which have memory images on disk

16. Schematic View of Swapping

17. Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium

18. Contiguous Allocation • Main memory usually is separated into two partitions: • Resident operating system, usually held in low memory with interrupt vector • User processes then held in high memory

19. Contiguous Allocation • Relocation registers are used to protect user processes from each other, and from changing operating-system code and data • A base register contains the value of smallest physical address • A limit register contains the range of logical addresses – each logical address must be less than the limit register • MMU maps logical address dynamically

20. Hardware Support for Relocation and Limit Registers

21. Contiguous Allocation (Cont) • Multiple-partition allocation • Hole – a block of available memory; holes of various size are scattered throughout memory • When a process arrives, it is allocated memory from a hole large enough to accommodate it • The operating system maintains information about:a) allocated partitions • b) free partitions (hole)

22. Contiguous Allocation (Cont) OS process 5 process 8 process 2 OS OS OS process 5 process 5 process 5 process 9 process 9 process 10 process 2 process 2 process 2

23. Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size Produces the smallest leftover hole Worst-fit: Allocate the largest hole; must also search entire list Produces the largest leftover hole How to satisfy a request of size n from a list of free holes

24. Dynamic Storage-Allocation Problem First-fit and best-fit work better than worst-fit in terms of speed and storage utilization

25. Fragmentation External Fragmentation– total memory space exists to satisfy a request, but it is not contiguous Internal Fragmentation– allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used

26. Fragmentation • Reduce external fragmentation by compaction • Shuffle memory contents to place all free memory together in one large block • Compaction is possible only if relocation is dynamic, and is done at execution time • I/O problem • Latch job in memory while it is involved in I/O • Do I/O only into OS buffers

27. Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium

28. Paging Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available Divide physical memory into fixed-sized blocks called frames(size is power of 2, between 512 bytes and 8,192 bytes) Divide logical memory into blocks of same size called pages Keep track of all free frames

29. Paging • To run a program of size n pages, need to find n free frames and load program • Set up a page table to translate logical to physical addresses • Internal fragmentation

30. Address Translation Scheme Address generated by CPU is divided into: Page number (p)– used as an index into a pagetable which contains base address of each page in physical memory Page offset (d)– combined with base address to define the physical memory address that is sent to the memory unit For given logical address space 2m and page size2n page number page offset p d m - n n

31. Paging Hardware

32. Paging Model of Logical and Physical Memory

33. Paging Example 32-byte memory and 4-byte pages

34. Free Frames After allocation Before allocation

35. Implementation of Page Table Page table is kept in main memory Page-table base register (PTBR)points to the page table Page-table length register (PRLR)indicates size of the page table In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.

36. Implementation of Page Table • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memoryor translation look-aside buffers (TLBs) • Some TLBs storeaddress-space identifiers (ASIDs)in each TLB entry – uniquely identifies each process to provide address-space protection for that process

37. Associative Memory Associative memory – parallel search Address translation (p, d) If p is in associative register, get frame # out Otherwise get frame # from page table in memory Page # Frame #

38. Paging Hardware With TLB

39. Effective Access Time Associative Lookup =  time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers Hit ratio =  Effective Access Time(EAT) EAT = (1 + )  + (2 + )(1 – ) = 2 +  – 

40. Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalidbit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page “invalid” indicates that the page is not in the process’ logical address space

41. Valid (v) or Invalid (i) Bit In A Page Table

42. Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes

43. Shared Pages • Private code and data • Each process keeps a separate copy of the code and data • The pages for the private code and data can appear anywhere in the logical address space

44. Shared Pages Example

45. Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium

46. Structure of the Page Table Hierarchical Paging Hashed Page Tables Inverted Page Tables

47. Hierarchical Page Tables Break up the logical address space into multiple page tables A simple technique is a two-level page table

48. Two-Level Page-Table Scheme

49. Two-Level Paging Example A logical address (on 32-bit machine with 1K page size) is divided into: a page number consisting of 22 bits a page offset consisting of 10 bits Since the page table is paged, the page number is further divided into: a 12-bit page number a 10-bit page offset where p1 is an index into the outer page table, and p2 is the displacement within the page of the outer page table

50. Address-Translation Scheme