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CBRAM ® Macro Embedded in a Body Sensor Node

CBRAM ® Macro Embedded in a Body Sensor Node. Nad Gilbert 1 , Yanqing Zhang 2 , John Dinh 1 , Benton Calhoun 2 ,and Shane Hollmer 1. 1 Adesto Technologies, Sunnyvale, CA 2 University of Virginia, Charlottesville, VA. Outline. Introduction - Ultra Low Power (ULP) CBRAM technology

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CBRAM ® Macro Embedded in a Body Sensor Node

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  1. CBRAM® Macro Embedded in a Body Sensor Node Nad Gilbert1, Yanqing Zhang2, John Dinh1, Benton Calhoun2,and Shane Hollmer1 1 Adesto Technologies, Sunnyvale, CA2 University of Virginia, Charlottesville, VA

  2. Outline • Introduction - Ultra Low Power (ULP) • CBRAM technology • CBRAM Macro Architecture • Energy Monitor • Sensing Circuit and Energy measurement Results • Write Circuit and Energy measurement Results • Body Sensor Node (BSN) concept and results • Die Photo • Comparison of macro to Prior work • Conclusion

  3. Introduction Typical Low Power Sensor Non-volatile Serial Flash The Missing ULP component TI SoC - Microcontroller, 12 bit ADC, temperature sensor (Demonstrated in ULP system), 128KB embedded FLASH (The Missing ULP component) Transceiver (Demonstrated in ULP system) Image courtesy of University of Washington Slide 2

  4. CBRAM Technology – Introduction < 20nm dimensions < 0.6V Operation Multi Level Cell < 1mA Write < 0.6V Write Conductive Bridging RAM (CBRAM) isa subset of Resistive RAM that is highly scalable low power high performance and can be integrated at Back-End-of-Line in a standard CMOS processes. <50ns Write Large Read Signal Verify During Write 1Transistor – 1 Resistor Cell (1T1R) DRAM Cost Structure Slide 3

  5. CBRAM Technology – Cross section Data is stored by modulating the resistance of the dielectric layer. Anode Cathode TEM Transistor Slide 4

  6. CBRAM Technology - Operation Program at 600mV and 400nA 1T1R Cell Anode Voltage (V) Tpg=14µs Cathode 400nA 0V Erase at 600mV and 200nA 1.2V Ter=2µs 200nA Voltage (V) Cathode Anode Time (µs) Slide 5

  7. CBRAM Macro Architecture • Dual bit line • Maximum device isolation • Dual supply domains • VDD (read) VCC (write) • Maximum usage of VCC • Minimized series resistance • Variable Word Line voltage Slide 6

  8. Voltage Across Cell ERASE HALF SEL BL 0 V 0 V 0.6 V 0.6 V 0.4V 0.6 V 0 V PROGRAM READ 0.6 V ~0.2V 0.4 V 0.4V 0 V 0 V Slide 7

  9. On Chip Energy Monitor VCCANALOG VREF Id(M1)=ILOAD M1 VMEAS • Dynamic Current monitor VLOADILOAD IBIAS IBIAS Energy monitor for each supply: VCC, VDD, and VWL Slide 8

  10. Sensing Circuit Pull Up Strength Programmable Pull up VDD as low as 0.3V Read Strobe SN Data Out Read Strobe Source follower Voltage limit Read Strobe 8:1 8:1 BLS BLAN WL Slide 9

  11. Measured results of Sense circuit 0.39 pJ/B Slide 10

  12. Write Circuit VCC as low as 0.6V Minimized Series resistance write path VCC VCC Data Dependent Program DinPROG drivers 1 Data Dependent Erase 1 OFF 1 DinERASE VWL WL BLAN BLS Complete Isolation when not selected Slide 11

  13. Measured Results of Program Operation Measured Program from CBRAM Array VCC=0.6V, VWL=0.6V, VDD=0.4V TPROG= 10us VMEAS (V), α IPROG Meas. Tot. E (pJ) leakage Current Time (μs) Slide 12

  14. Program Energy vs. Supply Sim. Energy/bit to PROG time @ const Ron Energy Minima at 1V Energy (pJ) Energy Minima at 0.7V VCC (V) Slide 13

  15. Measured Results of Write Operation Measured Erase from CBRAM Array VCC=0.6V, VWL=1V, VDD=0.4V TERASE=23us VMEAS (V), α IERASE leakage Current Meas. Tot. E (pJ) Time (μs) Slide 14

  16. Erase Energy vs. Supply Sim. Energy/bit to Erase time @ const Ron High Ron, Low energy Energy (pJ) VCC (V) Slide 15

  17. Body Sensor Node (BSN) Bus1[7:0] Bus2[7:0] ClkConfig DMEM CONFIG. SCAN CHAIN IMEM CONFIG. SCAN CHAIN CBRAM IMEM CBRAM DMEM EnConfig ConfigBits DIGITAL POWER MANAGER DMA SystemClk GPP RISC PROCESSOR ADC[7:0] CLOCK GEN. ClkScan RR ACCEL. AFIB ACCEL. IMEM DEBUG SCAN CHAIN EnScan SCAN CHAIN OUT ScanBits FIR ACCEL. ENV DET ACCEL. Accel. Clks ScanOutBits CBRAM was integrated with the Digital Platform only Slide 16

  18. BSN Results 6’hxx 6’h3E 6’hxx 6’h3E Enable[5:0] ClkGt[6:0] 7’hxx 7’h01 7’hxx 7’h01 Rst[6:0] 7’hxx 7’hxx 7’h01 7’h01 Bus1_connect[12:0] 13’hxxxx 13’h1F9F 13’hxxxx 13’h1F9F 13’hxxxx Bus2_connect[12:0] 13’hxxxx 13’h17FE 13’h17FE RISC_out[7:0] 8’hxx 8’h80 8’hxx 8’h80 Supply Status/Time Off/… On/10:45 AM Off/… On/5:55 PM Measured scan chain outputs showing correct operation of RISC processor from CBRAM, after power-down all day Slide 17

  19. BSN (digital) and CBRAM Die Photograph Timing Blocks And Config. Scan Chains 64kbCBRAMDMEM 64kbCBRAMIMEM DPM Prog. FIR DMA CLK GEN ENV DET Scan Out RR+ AFib RISC μProc Slide 18

  20. Comparison of Program Energy [3] [6] 1000 [4] 100 [5] Program Energy (pJ) 10 This work 1 Write Voltage (V) [3] 0.5V 4Mb embedded ReRAM [4] Flash with self-aligned split-gate cell [5] STT-MRAM [6] 4Mb embedded phase-change memory Slide 19

  21. Comparison of Technology Slide 20

  22. Conclusion • Device • 2 CBRAM macros embedded in BSN • Technology • 0.13 mm standard CMOS • Array size • 64 kb • Operating voltage • Integrated in BSN 0.5V • CBRAM macro 0.4 V read 0.6 V write • Operating Frequency • 200 kHz • Write energy • 8 pJ Slide 21

  23. Acknowledgements Ralph Williams and Derric Lewis Digital test interface of the CBRAM macro Altis Semiconductor Chip manufacturing DARPA Partial funding through an SBIR award Slide 22

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