1 / 39

Master Program (Laurea Magistrale) in Computer Science and Networking High Performance Computing Systems and Enabl

Master Program (Laurea Magistrale) in Computer Science and Networking High Performance Computing Systems and Enabling Platforms Marco Vanneschi. 4. Shared Memory Parallel Architectures 4.2. Interconnection Networks. Kinds of interconnection networks.

vea
Download Presentation

Master Program (Laurea Magistrale) in Computer Science and Networking High Performance Computing Systems and Enabl

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Master Program (Laurea Magistrale) in Computer Science and Networking High Performance ComputingSystems and EnablingPlatforms Marco Vanneschi 4. SharedMemoryParallelArchitectures 4.2. Interconnection Networks

  2. Kindsof interconnection networks • Main (contrasting) requirements: • High connectivity • High bandwidth, low latency • Low numberoflinks and limited pin count • Twoextremecases: • Bus (shared link) • Minumumcost and pin count • No parallelcommunications • Latency O(n) • Crossbar(full interconnection) • Maximumcost O(n2) and pin count • Maximumparallelism • Minumumconstantlatency M0 M1 M2 M3 For opposite reasons, bus and crossbar are not valid solutions for highly parallel architectures P0 P1 P2 P3 M0 M1 M2 M3 P0 P1 P2 P3 MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  3. Limiteddegreenetworks • Dedicatedlinksonly (no buses) • Reduced pin count • network degree = numberoflinks per node • Base latency O(log N), or O(N1/k) • Note: O(log N)is the best resultforstructureswithN arbitrarilylarge • base latency = latency in absenceofconflicts. Goal: mantain O(log N) latency in presenceofconflictstoo. • High bandwidth • Service timeisnotsignificantlyincreasedwrtcrossbar Basic idea: consider a crossbar-like structure composed of mtrees having the memory modules in the respective roots (latency: O(log n)) M0 M1 M2 M3 P0 P1 P2 P3 Merge all the trees in a limited degree structure, i.e. some sub-structures are in common to some trees. Possibly, apply topologycal transformations (e.g. transform trees into cubes). MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  4. Kindsoflimiteddegreenetworks • Indirect / multistagenetworks • Pathsbetweennodesconsistofintermediate nodes, calledswitchingnodes(or simplyswitches). Anycommunicationrequires a routingstrategythrough a pathcomposedofswitchingnodes. • Typicalexamples: • Butterfly (k-aryn-fly): fornetworksconnectingtwodistinctsetsofnodes (processing nodes and memorymodules in SMP) • Tree, fattree, generalizedfattree: fornetworksconnecting the samekindof processing nodes (NUMA) • Directnetworks • No intermediate switchingnodes. Some processing nodes are directlyconnectedtoothernodes (of the samekind, e.g. NUMA), in this case no routingisrequired. Routingstrategies are appliedtonodesthat are notdirectlyconnected. • Typicalexamples: • Ring • Multidimensionalmesh(k-ary n cube) • Directnetworks and the varietiesoftrees are appliedtodistributedmemoryarchitecturesaswell. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  5. k-aryn-flynetworks C0 C1 C2 C3 C4 C5 C6 C7 S0 S1 S2 S3 S4 S5 S6 S7 n = 3 • Butterfliesofdimensionn and arietyk. • Example: 2-ary 3-cube for 8 + 8nodes:  k = 2 Number of processing nodes: N = 2 kn e.g., knprocessors (Ci), kn memory modules (Sj) in SMP. Network degree = 2k. Network distance (constant): d = n proportional to the base latency. Thus, base latency = O(log N). There is one and only one unique path between any Ci and any Sj . It is exploited in deterministic routing. Processing node Switchingnode MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  6. Formalization: binarybutterfly (2-ary n-fly) • Connects2nprocessing nodesto2nprocessing nodes, throughnlevelsofswitchingnodes • Processing nodes are connectedto the first and the last levelrespectively. • Eachlevelcontains2n-1switchingnodes • Total numberofswitchingnodes = n 2n-1= O(N log N) • Total numberoflinks = (n – 1) 2n = O(N log N) • wrt O(N2) ofcrossbar. Note: the FFT (Fast Fourier Transform) algorithmhas a binarybutterflytopology. Itreduces the complexityof the Discrete Fourier TransformfromO(N2)toO(N log N) steps. The data-parallelimplementationof FFT hascompletiontimeO(log N) withO(N) virtualprocessors. The stencil at i-thstepisexactlydescribedby the topologyof the butterflyi-thlevel. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  7. Formalization: binarybutterfly (2-ary n-fly) Connectivityrule: • Eachswitchingnodeisdefinedby the coordinates(x, y),where • 0  x  2n-1is the rowidentifier, • 0  y  n-1 is the columnidentifier. • Genericswitchingnode(i, j),with0  j  n-2,isconnectedtotwoswitchingnodesdefinedasfollows: • (i, j + 1)through the so called “straight link” • (h, j + 1) through the so called “oblique link”, wherehissuchthat abs (h – i) = 2n-j-2 i.e. the binaryrepresentationofhdiffersfrom the binayrepresentationofi onlyfor the j-thbit startingfrom the mostsignificant bit. • The connectivityruledefines the deterministic, minimal routingalgorithm. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  8. Formalization: binarybutterfly (2-ary n-fly) Recursiveconstruction: • forn = 1: butterlyis just oneswitchingnodewith 2 input links and 2 output links; • given the ndimensionbutterfly, the (n+1) dimensionbutterflyisobtainedapplying the following procedure: • twondimensionbutterflys are considered, “oneover the other”, so obtaining the nfinallevels, eachofthemcomposedof2nswitches; • a levelof2nswitchesisadded at the left; • the first levelswitches are connectedto the secondlevelswitchesaccording the connectivityrule, in ordertogrant the full reachabilityof the structure. • Formaltransformationsofbinarybutterfliesintobinaryhypercubes are known. • Formalization can begeneralizedtoanyarietyk. • Manyothermultistagenetworks (Omega, Benes, and so on) are definedasvariantsofk-aryn-fly. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  9. Routingalgorithmfork-aryn-fly The deterministic, minimal algorithmderivesfrom the connectivityrule. Fork = 2, consider the binaryrepresentationof the source and destination processing nodeidentifiers, e.g. C3 = (011) and S6 = (110). Theseidentifiers are contained in the message sent through the network. • Once identified the first switch, the algorithmevolvesthroughn steps. At i-thstep the switchcompares the i-thbit of source and destinationidentifiers, startingfrom the mostsignificant bit: ifthey are equal the messageis sent to the straightlink, otherwiseto the oblique link. • The last switchrecognizes the destination just accordingto the leastsignificant bit ofdestinationidentifier. • Forrouting in the opposite direction (from S to C), the binaryidentifiers are analyzed in reverse order, startingfrom the secondleastsignificant bit. The algorithmisgeneralizedtoanyk. Othernon-minimalroutingstrategies can bedefinedfork-ary n –flynetworks, notablyadaptiveroutingaccordingtonetwork loadand/or link availability. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  10. k-aryn-cubenetworks • Cubes of dimensionn and arietyk. • Generalization of ring (toroidal) structures. k = 4, n = 1 k = 4, n = 2 k = 4, n = 3 No switch nodes. In principle, the processing nodes are the nodes of the network structure. In practice, the network nodes are interfaces of the processing nodes. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  11. k-aryn-cubes • Numberof processing nodes: N = kn. • Network degree = 2n. • Averagedistance = O(k n) : proportionalto base latency. • For a givenN (e.g. N = 1024), wehavetwotypicalchoices: • nas low aspossible (e.g. 32-ary 2-cube) • nas high aspossible (e.g. 2-ary 10-cube) • Forlow-dimensioncubes: distance = O(N1/k) • Forhigh-dimensioncubes: distance = O(log N) • Despitethisdifference in the orderofmagnitude, the detailedevaluationoflatencyis in favouroflow-dimensioncubes: • High-dimensioncubesare criticalfrom the pin count and link costviewpoint: in practice, they are forcedtousefew-bitparallellinks (serial linksare common). Thisgreatlyincreases the latencyvalue (multiplicativeconstantis high). • Low-dimensioncubes(n = 2, 3) are more feasiblestructures, and theirlatencytendstobelower (low valuesof the multiplicativeconstant) formanyparallelprogramswrittenaccordingto the knownformsofparallelism (farm, data-parallel). MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  12. k-aryn-cubes • Deterministic routing: dimensional • Example for k = 2: Sorce = (x1, y1), Destination (x2, y2) • Routing steps along the first dimension from (x1, y1) to (x2, y1) • Routing steps along the second dimension from (x2, y1) to (x2, y2) • Application of k-ary n-cubes: NUMA MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  13. Switch node Processing node N6 N0 N2 N4 N5 N1 N3 N7 Trees Consider a binary tree multistage network connecting N nodes of the same kind as leafes of the tree: Ariety k (e.g. k = 2) Dimension n Number of nodes: N = kn Average distance: dnet 1,9  n Routing algorithm: tree visit Base latency = O( log N). However, the number of conflicts is relatively high: as higher as the distance increases. The problem can be solved by increasing the bandwidth (i.e. parallelism of links) as we move from the leaves towards the root: we obtain the so called FAT TREE network. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  14. N0 N2 N4 N6 N1 N3 N5 N7 Fattrees 4 links in parallel 2 links in parallel 1 link Links in parallel are used as alternative links for distinct messages flowing between the same switching nodes, thus reducing the conflicts. If the bandwidth doubles at each level from the leafs to the root, then the conflict probability becomes negligible, provided that the switching node has a parallel internal behaviour. The solution to the pin count and link cost problem, and to the switching node bandwidth problem, is the Generalized Fat Tree, based on k-ary n-fly structures. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  15. GeneralizedFatTree The requirement is that the i-th level behaves as a 2i x 2i crossbar, without pin count problems for high value of i. These limited degree crossbars are implemented by a k-ary n-fly structure with a single set of processing nodes: Routing algorithm: tree routing algorithm + dynamic adaptivity to link availability. Interesting network, also because it can be exploited, at the same time, as a Fat Tree and as a butterfly itself, provided that the switching node implements both routingalgorithms. Typical application: in SMP as processor-to-memory network (butterfly) and as processor-to-processor network (Fat Tree). N0 N1 N2 N3 N4 N5 N6 Basic scheme for the most interesting networks: Myrinet, Infiniband. N7 MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms 3-rd level switch 2-nd level switch 1-st level switch

  16. Flow controlof interconnection networksforparallelarchitectures • Flow controltechniques: management ofnetworksresources, i.e. links, switchingnodes, internalbuffers, etc. • Packet-based flow control: at eachswitchingnodeof the routingpath, the wholepacketmustbereceived, and buffered, beforeitis sent towards the nextswitchingnode. • Packets are the routingunits, and distinctspackets can followdistinctpaths in parallel. • Especially in parallelarchitectures, the single packettransmission can befurtherparallelized: wormhole flow controlstrategy: • packets are decomposedintoflits, • flitsof the samepacket are propagatedin pipeline, thusreducing the latencyfromO(pathlengthmessagesize)toO(pathlength + messagesize),providedthatthis fine grainparallelismisefficientlyexploitedby the switchingnodes. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  17. Wormhole flow control • The routing unit is the packet as well: all the flits of the same packet follow exactly the same path. • The first flit must contain the routing information (packet heading). • In general, with w-bit parallel links (e.g. w = 32 bit), the flit size is w bits (possibly, 2w bits). • The minimum buffering capacity inside a switching node is one flit per link (instead of a packet per link): this contributes to the very efficient firmware implementation of switching nodes (one clock cycle service time and internal latency). • Implemented in most powerful networks. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  18. Implementationof a wormholeswitchingnode SWi SWi1 Routing and flow control IN11 OUT11 IN12 OUT12 SWi2 Routing and flow control OUT21 IN21 OUT22 IN22 MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  19. Implementationof a wormholeswitchingnode Dedicated links with level-transition RDY-ACK interfaces (see firmware prerequisites) Distinct units for the two network directions. At every clock cycle, control the presence of incoming messages and, for heading-flits, determine the output interface according to the routing algorithm. The heading-flit is sent if the output interface has not been booked by another packet. SWi SWi1 Routing and flow control IN11 OUT11 IN12 OUT12 Once the heading-flit of a packet has been sent to the proper output interface, then the rest of the packet follows the heading-flit. SWi2 Routing and flow control OUT21 IN21 Adaptive routing is implemented according to ACK availability (and possibly time-outs). OUT22 IN22 MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  20. Exercize Assume that a wormoholeGeneralizedFatTree network, witharietyk = 2 and n = 8, isused in a SMP architecturewith a doublerole: a) processor-to-memory interconnection, and b) processor-to-processor interconnection. The firmwaremessagescontain in the first word: routing information (source identifier, destinationidentifier), messagetype (a or b), messagelength in words. Link and flitssizeisone word. Describe the detailed (e.g., at the clock cyclegrain) behaviourof a switchingnode. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  21. Latencyofcommunicationstructureswithpipelined flow control Pipelined communications occur in structures including wormhole networks and other computing structures (interface units, interleaved memories, etc). • Wewishtoevaluate the latencyofsuch a pipelinedstructurewithdunitsforfirmwaremessagesoflengthmwords. • Let’s assume that • wormholeflitisequalto a word, • everyunitshas clock cyclet, • every link hastransmissionlatencyTtr. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  22. Latencyofcommunicationstructureswithpipelined flow control Example with d = 4 units and m = 5 words per message (packet) “hop” Tlat-pipe = (m – 1) 2 (t + Ttr) + (d – 1) (t + Ttr) = (2m + d – 3) (t + Ttr) Let’s denote: thop = t + Ttr called “hop latency” (latency of a single “hop”): Tlat-pipe = (2m + d – 3) thop Ttr t MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms (d – 1) (t + Ttr) (m – 1) 2 (t + Ttr)

  23. Memoryaccesslatencyevaluation Assumptions: • All-cache architecture • Cache block size s • Shared main memory, each memory macro-module is s-way interleaved (or s long word) • Wormhole, n dimension, binary Generalized Fat Tree network • Link size = flit size = one word • D-RISC Pipelined CPU Let’s evaluate: • Base latency of a cache block transfer (absence of conflicts) • Under-load latency of a cache block transfer (presence of conflicts) MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  24. Schemeof the system tobeevaluated . . . msg type 0 M0 M1 M7 msg type 1 IM Request of a remote block transfer (firmware msg 0) : latency T0 and block transfer (firmware msg 1): latency T1 W SWdnet SWdnet-1 Generalized Fat Tree k = 2 n = 8 Base latency for a remote block transfer: SWdnet-2 ta.-base = T0 + T1 . . . Let’s denote: dnet = average network distance (e.g., with n = 8, dnet = 15 in the worst case, dnet = 8 in the best case) SW3 SW2 CPU SW1 MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms SW0 W MINF CD

  25. Firmwaremessages Message format: sequence of words Heading: 1 word Value, first word Value, second word … Flow control information Msg type Routing information • Headingisinserted or removedby the interface unit W between CPU and network: • 4 bits: messagetype • 8 bits: source nodeidentifier • 8 bits: destinationnodeidentifier; in this case, itis a memorymacro-module, identifiedby the least 8 bitsofphysicaladdress (in SMP), or the most 8 significant bit (in a NUMA architecture) – examplefor 256 nodes and memorymacro-modules • 8 bit: messagelength (numberofwords) • 4 bits: otherfunctions • Messagetypesforthisexample: • Msg 0: requestof a block transfer to the remote memory • Msg 1: block valuefrom the remote memory MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  26. Firmwaremessages and theirlatencies Msg 0: • Value: Physicaladdress relative to the memorymodule: e.g. 1 word • Messagelength, includingheading: m = 2 words Itpropagatesin pipeline throughCPU-MINF, WCPU, network, WMEM, Memory Interface: distance d = dnet + 4 Latencyofmessage 0 (applying the pipelinedcommunication formula): T0 = (2m + d – 3) thop= (5 + dnet) thop MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  27. Firmwaremessages and theirlatencies Msg 1: • Value: Access outcomecontrol information: 1 word • Value: Block value: swords • Messagelength, includingheading: m = 2 + swords Thismessageimplies the readingfrom the interleavedmemorymodule, whichincludes the followingsequentialpaths: • requestfromMemory Interface tomodules: thop • access in parallelto the s interleavedmodules: tM • swords in parallelfrommodulestoMemory Interface: thop At thispoint, the result (outcome, block value) flowsin pipeline throughMemory Interface, WMEM, network, WCPU, CPU-MINF: distance d = dnet + 4 Latencyofmessage 1 (applying the pipelinedcommunication formula): T1 = 2 thop + tM + (2m + d – 3) thop= 2 thop + tM + (2s + 5 + dnet) thop MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  28. Base latency As a result, the base accesslatencyisgivenby: ta-base = T0 + T1 =  c + 2(s + dnet) thop + tM wherecis a system-dependentconstant (= 12 in thisexample). For a binaryFatTree network: dnet = d n wheren = log2N, and disanapplication-dependentparameter in the range 1 d < 2 accordingto the localityof the internodecommunications, thusdepending on the allocationofapplicationprocesses. Forexample, withdnet = 15, s = 8, thop = 5t, tM = 50t: ta-base = 290t + 50t = 340t. Withdnet = 8, s = 8, thop = 5t, tM = 50t: ta-base = 240t + 50t = 290t. Evenwith a rather slow memory, the impact of the network latency on memoryaccesslatencyis the mostmeaningful. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  29. Under-loadlatency: queueingmodeling • The system ismodeledas a queueing system, where • processing nodes are clients • sharedmemorymodules are servers, including the interconnection structure • e.g. M/D/1 queueforeachmemorymodule Mj Response Time P0 Pi Pn-1 . . . . . . 0 1 server utilization factor (r) • The memory access latency is the server Response Time. • Critical dependency on the server utilization factor: a measure of memory modules congestion, or a measure of processors “conflicts” to access the same memory module • The interarrival time has to be taken as low as possible: the importance of local accesses, thus the importance of the best exploitation of local memories (NUMA) and caches (SMP). MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  30. Under-loadlatency: queueingmodeling • Each server has an average number p of clients, where p is a parameter (N) representing the average number of processing nodes that share the same memory module. • In a SMP architecture, according to the costant probability that any processor accesses any memory macro-module: p = N / m • In a NUMA architecture, p is application-dependent, though p < N especially for structured parallel programs that are characterized by some communication locality. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  31. Under-loadlatency: queueingmodeling • With a Fat Tree network, it is acceptable to assume that, especially for small p, the the effect of conflicts over networks links is negligible compared to the effect of conflicts on memory modules. • Let Tpbe the average processing time of the generic processor between two consecutive accesses to remote memory. Let’s assume that the corresponding random variable is exponentially distributed. • The memory access time, i.e. the server response time RQ, is the solution of the following system of equations (see the client-server modeling in the ILP part of the course): MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  32. Under-loadlatency: queueingmodeling A good approximation for WQ is given by the M/D/1 queue: ta-base ta-base RQ is the one and only one real solution of a second degree equation with real coefficients. In the following, the evaluation will be expressed graphically according to the parameters: p, Tp, N, s, d, thop, tM. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  33. Under-loadlatency: evaluation p variable; s = 8, d = 1, thop = 5 t, tM = 10 t, N = 64, Tp = 2000 t: n = 6, ta-base = 210 t p is one of the most critical parameters. Good performances are achieved for p < 8: in NUMA architectures if applications have high communication –locality, in SMP for high ratio N/m. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  34. Under-loadlatency: evaluation Tpvariable; s = 8, d = 1, thop = 5 t, tM = 10 t, N = 64, p = 4: n = 6, ta-base = 210 t Cache block access latency / t Tp is a meaningful parameter as well. For coarse grain applications, RQtends to the ta-basevalue, i.e. the memory conflicts are negligible. For fine grain applications, memory conflicts have a relevant negative impact. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  35. Under-loadlatency: evaluation p, Tpvariables; s = 8, d = 1, thop = 5 t, tM = 10 t, N = 64: n = 6, ta-base = 210 t Cache block access latency / t Combined effect of p and Tp. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  36. Under-loadlatency: evaluation N variable; s = 8, d = 1, thop = 5 t, tM = 10 t, N = 64, p = 4, Tp = 2000 t: for 8 ≤ N ≤ 256, 3 ≤ n ≤ 8, 180t≤ ta-base≤ 230t. Cache block access latency / t In this evaluation, the true parallelism degree is p, not N. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  37. Under-loadlatency: evaluation svariable; d = 1, thop = 5 t, tM = 10 t, N = 64, p = 4, Tp = 2000 t: for 2 ≤ s ≤ 16, 150t≤ ta-base≤ 290t; n = 6. Cache block access latency / t Though large blocks increase RQ, they can be beneficial: a double value of RQ is compensated by a less number of remote accesses. The positive impact of wormhole flow control is remarkable in this evaluation. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  38. Under-loadlatency: evaluation dvariable; s = 8, thop = 5 t, tM = 10 t, N = 64, p = 4, Tp = 2000 t: for 1 ≤ d ≤ 2, 210t≤ ta-base≤ 270t; n = 6. Cache block access latency / t d has not a meaningful impact for low values of p. The network path length tends to have a negligible impact wrt the impact of the number of nodes in conflict. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

  39. Under-loadlatency: evaluation tM variable; s = 8, d = 1, thop = 5 t, N = 64, p = 4, Tp = 2000 t: n = 6; for 10 t≤ tM≤ 1000 t , 210t≤ ta-base≤ 1200t. Cache block access latency / t “Slow” memories have a relevant, negative impact, while the impact is limited for memory clock cycle of few 10s t. MCSN - M. Vanneschi: High Performance Computing Systems and Enabling Platforms

More Related