Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design

1. Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate • Dynamic circuit operation is divided into two modes: precharge and evaluate Dynamic logic

3. What if pulldown network is ON during precharge? Contention arises because both pMOS and nMOS will be ON Use series evaluation transistor to prevent fight. What if the input is ON during precharge?

4. Logic effort for dynamic circuits Very fast with very low logical effort

5. Dynamic gates require monotonically rising inputs during evaluation 0 → 0 0 → 1 1 → 1 But not 1 → 0 Dynamic circuits have a problem: Monotonicity requirement

6. But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! Implications of Monotonicity

7. Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Domino Logic

8. Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic Domino optimizations 8-input multiplexer built from two 4-input dynamic multiplexers

9. Domino only performs noninverting functions: AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs Dual-Rail Domino

10. Dynamic node floats high during evaluation Transistors are leaky (IOFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation Leakage problems

11. Solution: add secondary precharge transistors • Typically need to precharge every other node • Big load capacitance CY helps as well Charge sharing • Dynamic gates suffer from charge sharing

12. Domino logic is attractive for high-speed circuits 1.5 – 2x faster than static CMOS But many challenges: Monotonicity, leakage, charge sharing, noise, and high dynamic power Widely used in high-performance microprocessors Domino Summary Circuit Families • Static CMOS • Ratioed Circuits • Cascode Voltage Switch Logic • Pass-transistor Circuits • Dynamic Circuits